src/mainboard/tyan/s2891/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #include "northbridge/amd/amdk8/setup_resource_map.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 static void memreset_setup(void)
  32 {
  33 }
  34
  35 static void memreset(int controllers, const struct mem_controller *ctrl)
  36 {
  37 }
  38
  39 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  40 {
  41         /* nothing to do */
  42 }
  43
  44 static inline int spd_read_byte(unsigned device, unsigned address)
  45 {
  46         return smbus_read_byte(device, address);
  47 }
  48
  49 #include "northbridge/amd/amdk8/raminit.c"
  50 #include "northbridge/amd/amdk8/coherent_ht.c"
  51 #include "lib/generic_sdram.c"
  52
  53  /* tyan does not want the default */
  54 #include "resourcemap.c"
  55
  56 #include "cpu/amd/dualcore/dualcore.c"
  57
  58 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  59 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  60
  61 #include "cpu/amd/car/post_cache_as_ram.c"
  62
  63 #include "cpu/amd/model_fxx/init_cpus.c"
  64
  65 #include "northbridge/amd/amdk8/early_ht.c"
  66
  67 static void sio_setup(void)
  68 {
  69         uint32_t dword;
  70         uint8_t byte;
  71
  72         /* subject decoding*/
  73         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  74         byte |= 0x20;
  75         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  76
  77         /* LPC Positive Decode 0 */
  78         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  79         /* Serial 0, Serial 1 */
  80         dword |= (1<<0) | (1<<1);
  81         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  82
  83 #if 1
  84         /* s2891 has onboard LPC port 80 */
  85         /*Hope I can enable port 80 here
  86         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  87         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  88         dword |= (1<<16);
  89         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
  90 #endif
  91 }
  92
  93 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  94 {
  95         static const uint16_t spd_addr [] = {
  96                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  97                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  98 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  99                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 100                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 101 #endif
 102         };
 103
 104         int needs_reset;
 105         unsigned bsp_apicid = 0;
 106
 107         struct mem_controller ctrl[8];
 108         unsigned nodes;
 109
 110         if (!cpu_init_detectedx && boot_cpu()) {
 111                 /* Nothing special needs to be done to find bus 0 */
 112                 /* Allow the HT devices to be found */
 113
 114                 enumerate_ht_chain();
 115
 116                 sio_setup();
 117         }
 118
 119         if (bist == 0) {
 120                 bsp_apicid = init_cpus(cpu_init_detectedx);
 121         }
 122
 123 //      post_code(0x32);
 124
 125         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 126         uart_init();
 127         console_init();
 128
 129         /* Halt if there was a built in self test failure */
 130         report_bist_failure(bist);
 131
 132         setup_s2891_resource_map();
 133 #if 0
 134         dump_pci_device(PCI_DEV(0, 0x18, 0));
 135         dump_pci_device(PCI_DEV(0, 0x19, 0));
 136 #endif
 137
 138         needs_reset = setup_coherent_ht_domain();
 139
 140         wait_all_core0_started();
 141 #if CONFIG_LOGICAL_CPUS==1
 142         // It is said that we should start core1 after all core0 launched
 143         start_other_cores();
 144         wait_all_other_cores_started(bsp_apicid);
 145 #endif
 146
 147         needs_reset |= ht_setup_chains_x();
 148
 149         needs_reset |= ck804_early_setup_x();
 150
 151         if (needs_reset) {
 152                 printk(BIOS_INFO, "ht reset -\n");
 153                 soft_reset();
 154         }
 155
 156         allow_all_aps_stop(bsp_apicid);
 157
 158         nodes = get_nodes();
 159         //It's the time to set ctrl now;
 160         fill_mem_ctrl(nodes, ctrl, spd_addr);
 161
 162         enable_smbus();
 163 #if 0
 164         dump_spd_registers(&cpu[0]);
 165 #endif
 166 #if 0
 167         dump_smbus_registers();
 168 #endif
 169
 170         memreset_setup();
 171         sdram_initialize(nodes, ctrl);
 172
 173 #if 0
 174         print_pci_devices();
 175 #endif
 176
 177 #if 0
 178         dump_pci_devices();
 179 #endif
 180
 181         post_cache_as_ram();
 182 }
 183