2 * Tyan S2891 needs a different resource map
6 static void setup_s2891_resource_map(void)
8 static const unsigned int register_values[] = {
10 /* Careful set limit registers before base registers which contain the enables */
11 /* DRAM Limit i Registers
20 * [ 2: 0] Destination Node ID
30 * [10: 8] Interleave select
31 * specifies the values of A[14:12] to use with interleave enable.
33 * [31:16] DRAM Limit Address i Bits 39-24
34 * This field defines the upper address bits of a 40 bit address
35 * that define the end of the DRAM region.
37 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
38 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
39 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
40 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
41 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
42 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
43 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
44 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
45 /* DRAM Base i Registers
57 * [ 1: 1] Write Enable
61 * [10: 8] Interleave Enable
63 * 001 = Interleave on A[12] (2 nodes)
65 * 011 = Interleave on A[12] and A[14] (4 nodes)
69 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
71 * [13:16] DRAM Base Address i Bits 39-24
72 * This field defines the upper address bits of a 40-bit address
73 * that define the start of the DRAM region.
75 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
76 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
77 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
78 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
79 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
80 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
81 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
82 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
86 /* Memory-Mapped I/O Limit i Registers
95 * [ 2: 0] Destination Node ID
105 * [ 5: 4] Destination Link ID
112 * 0 = CPU writes may be posted
113 * 1 = CPU writes must be non-posted
114 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
115 * This field defines the upp adddress bits of a 40-bit address that
116 * defines the end of a memory-mapped I/O region n
118 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
119 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
120 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
121 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
122 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
123 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
124 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
125 // PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
127 /* Memory-Mapped I/O Base i Registers
136 * [ 0: 0] Read Enable
139 * [ 1: 1] Write Enable
140 * 0 = Writes disabled
142 * [ 2: 2] Cpu Disable
143 * 0 = Cpu can use this I/O range
144 * 1 = Cpu requests do not use this I/O range
146 * 0 = base/limit registers i are read/write
147 * 1 = base/limit registers i are read-only
149 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
150 * This field defines the upper address bits of a 40bit address
151 * that defines the start of memory-mapped I/O region i
153 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
154 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
155 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
156 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
157 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
158 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
159 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
160 // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
164 /* PCI I/O Limit i Registers
169 * [ 2: 0] Destination Node ID
179 * [ 5: 4] Destination Link ID
185 * [24:12] PCI I/O Limit Address i
186 * This field defines the end of PCI I/O region n
189 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
190 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
191 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
192 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
194 /* PCI I/O Base i Registers
199 * [ 0: 0] Read Enable
202 * [ 1: 1] Write Enable
203 * 0 = Writes Disabled
207 * 0 = VGA matches Disabled
208 * 1 = matches all address < 64K and where A[9:0] is in the
209 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
211 * 0 = ISA matches Disabled
212 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
213 * from matching agains this base/limit pair
215 * [24:12] PCI I/O Base i
216 * This field defines the start of PCI I/O region n
219 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
220 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
221 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
222 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
224 /* Config Base and Limit i Registers
229 * [ 0: 0] Read Enable
232 * [ 1: 1] Write Enable
233 * 0 = Writes Disabled
235 * [ 2: 2] Device Number Compare Enable
236 * 0 = The ranges are based on bus number
237 * 1 = The ranges are ranges of devices on bus 0
239 * [ 6: 4] Destination Node
249 * [ 9: 8] Destination Link
255 * [23:16] Bus Number Base i
256 * This field defines the lowest bus number in configuration region i
257 * [31:24] Bus Number Limit i
258 * This field defines the highest bus number in configuration region i
261 // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
262 // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
263 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
264 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
270 max = sizeof(register_values)/sizeof(register_values[0]);
271 setup_resource_map(register_values, max);