1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_isa;
10 extern unsigned char bus_ck804_0; //1
11 extern unsigned char bus_ck804_1; //2
12 extern unsigned char bus_ck804_2; //3
13 extern unsigned char bus_ck804_3; //4
14 extern unsigned char bus_ck804_4; //5
15 extern unsigned char bus_ck804_5; //6
16 extern unsigned char bus_8131_0; //7
17 extern unsigned char bus_8131_1; //8
18 extern unsigned char bus_8131_2; //9
19 extern unsigned apicid_ck804;
20 extern unsigned apicid_8131_1;
21 extern unsigned apicid_8131_2;
23 extern unsigned sbdn3;
27 static void *smp_write_config_table(void *v)
29 static const char sig[4] = "PCMP";
30 static const char oem[8] = "COREBOOT";
31 static const char productid[12] = "S2891 ";
32 struct mp_config_table *mc;
35 unsigned char bus_num;
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
39 memset(mc, 0, sizeof(*mc));
41 memcpy(mc->mpc_signature, sig, sizeof(sig));
42 mc->mpc_length = sizeof(*mc); /* initially just the header */
44 mc->mpc_checksum = 0; /* not yet computed */
45 memcpy(mc->mpc_oem, oem, sizeof(oem));
46 memcpy(mc->mpc_productid, productid, sizeof(productid));
49 mc->mpc_entry_count = 0; /* No entries yet... */
50 mc->mpc_lapic = LAPIC_ADDR;
55 smp_write_processors(mc);
61 /* define bus and isa numbers */
62 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
63 smp_write_bus(mc, bus_num, "PCI ");
65 smp_write_bus(mc, bus_isa, "ISA ");
67 /*I/O APICs: APIC ID Version State Address*/
73 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
75 res = find_resource(dev, PCI_BASE_ADDRESS_1);
77 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
80 /* Initialize interrupt mapping*/
83 pci_write_config32(dev, 0x7c, dword);
86 pci_write_config32(dev, 0x80, dword);
89 pci_write_config32(dev, 0x84, dword);
93 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
95 res = find_resource(dev, PCI_BASE_ADDRESS_0);
97 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
100 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
102 res = find_resource(dev, PCI_BASE_ADDRESS_0);
104 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
110 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
111 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
113 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x2);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_ck804, 0x3);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_ck804, 0x4);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_ck804, 0x6);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_ck804, 0x7);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_ck804, 0x8);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_ck804, 0xc);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_ck804, 0xd);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_ck804, 0xe);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
124 // Onboard ck804 smbus
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
127 // Onboard ck804 USB 1.1
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
130 // Onboard ck804 USB 2
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
133 // Onboard ck804 SATA 0
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
136 // Onboard ck804 SATA 1
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
155 //Onboard Broadcom NIC
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
162 //Slot 4 PCIX 133/100/66
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
167 //Slot 3 PCIX 133/100/66 SoDIMM PCI
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
172 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
173 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
174 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
175 /* There is no extension information... */
177 /* Compute the checksums */
178 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
179 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
180 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
181 mc, smp_next_mpe_entry(mc));
182 return smp_next_mpe_entry(mc);
185 unsigned long write_smp_table(unsigned long addr)
188 v = smp_write_floating_table(addr);
189 return (unsigned long)smp_write_config_table(v);