3 #include <device/pci_def.h>
4 #include <device/pci_ids.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include "pc80/mc146818rtc_early.c"
10 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
11 #include "northbridge/amd/amdk8/early_ht.c"
12 #include "cpu/x86/lapic/boot_cpu.c"
13 #include "northbridge/amd/amdk8/reset_test.c"
15 static void sio_setup(void)
22 byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
24 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
26 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
27 dword |= (1<<0) | (1<<1);
28 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
31 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
33 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
39 #if CONFIG_LOGICAL_CPUS==1
40 #include "cpu/amd/dualcore/dualcore_id.c"
43 static unsigned long main(unsigned long bist)
45 #if CONFIG_LOGICAL_CPUS==1
46 struct node_core_id id;
50 /* Make cerain my local apic is useable */
53 #if CONFIG_LOGICAL_CPUS==1
54 id = get_node_core_id_x();
55 /* Is this a cpu only reset? */
56 if (cpu_init_detected(id.nodeid)) {
59 /* Is this a cpu only reset? */
60 if (cpu_init_detected(nodeid)) {
62 if (last_boot_normal()) {
69 /* Is this a secondary cpu? */
71 if (last_boot_normal()) {
78 /* Nothing special needs to be done to find bus 0 */
79 /* Allow the HT devices to be found */
88 /* Is this a deliberate reset by the bios */
89 if (bios_reset_detected() && last_boot_normal()) {
92 /* This is the primary cpu how should I boot? */
93 else if (do_normal_boot()) {
100 asm volatile ("jmp __normal_image"
102 : "a" (bist) /* inputs */
107 //CPU reset will reset memtroller ???
108 asm volatile ("jmp __cpu_reset"
110 : "a"(bist) /* inputs */