src/mainboard/tyan/s2891/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14
  15 #define K8_HT_FREQ_1G_SUPPORT 0
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28 #include "cpu/amd/dualcore/dualcore.c"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  33
  34 static void hard_reset(void)
  35 {
  36         set_bios_reset();
  37
  38         /* full reset */
  39         outb(0x0a, 0x0cf9);
  40         outb(0x0e, 0x0cf9);
  41 }
  42
  43 static void soft_reset(void)
  44 {
  45         set_bios_reset();
  46 #if 1
  47         /* link reset */
  48         outb(0x02, 0x0cf9);
  49         outb(0x06, 0x0cf9);
  50 #endif
  51 }
  52
  53 static void memreset_setup(void)
  54 {
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59 }
  60
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63         /* nothing to do */
  64 }
  65
  66 static inline int spd_read_byte(unsigned device, unsigned address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #define QRANK_DIMM_SUPPORT 1
  72 #include "northbridge/amd/amdk8/raminit.c"
  73 #include "northbridge/amd/amdk8/coherent_ht.c"
  74 #include "sdram/generic_sdram.c"
  75
  76 /* tyan does not want the default */
  77 #include "resourcemap.c"
  78
  79 #define FIRST_CPU       1
  80 #define SECOND_CPU 1
  81 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  82
  83 #define CK804_NUM 1
  84 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  85 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  86
  87 static void main(unsigned long bist)
  88 {
  89         static const struct mem_controller cpu[] = {
  90 #if FIRST_CPU
  91                 {
  92                         .node_id = 0,
  93                         .f0 = PCI_DEV(0, 0x18, 0),
  94                         .f1 = PCI_DEV(0, 0x18, 1),
  95                         .f2 = PCI_DEV(0, 0x18, 2),
  96                         .f3 = PCI_DEV(0, 0x18, 3),
  97                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
  98                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
  99                 },
 100 #endif
 101 #if SECOND_CPU
 102                 {
 103                         .node_id = 1,
 104                         .f0 = PCI_DEV(0, 0x19, 0),
 105                         .f1 = PCI_DEV(0, 0x19, 1),
 106                         .f2 = PCI_DEV(0, 0x19, 2),
 107                         .f3 = PCI_DEV(0, 0x19, 3),
 108                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 109                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 110                 },
 111 #endif
 112         };
 113
 114         int needs_reset;
 115 #if CONFIG_LOGICAL_CPUS==1
 116         struct node_core_id id;
 117 #else
 118         unsigned nodeid;
 119 #endif
 120
 121         if (bist == 0) {
 122                 k8_init_and_stop_secondaries();
 123         }
 124
 125         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 126         uart_init();
 127         console_init();
 128
 129         /* Halt if there was a built in self test failure */
 130         report_bist_failure(bist);
 131
 132         setup_s2891_resource_map();
 133
 134         needs_reset = setup_coherent_ht_domain();
 135
 136         needs_reset |= ht_setup_chains_x();
 137
 138         needs_reset |= ck804_early_setup_x();
 139
 140         if (needs_reset) {
 141                 print_info("ht reset -\r\n");
 142                 soft_reset();
 143         }
 144
 145         enable_smbus();
 146
 147         memreset_setup();
 148         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 149
 150 }