3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
29 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
35 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
36 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
37 uses LINUXBIOS_EXTRA_VERSION
47 uses DEFAULT_CONSOLE_LOGLEVEL
48 uses MAXIMUM_CONSOLE_LOGLEVEL
49 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
50 uses CONFIG_CONSOLE_SERIAL8250
51 uses CONFIG_CONSOLE_BTEXT
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
64 uses ENABLE_APIC_EXT_ID
68 uses CONFIG_PCI_64BIT_PREF_MEM
70 uses HT_CHAIN_UNITID_BASE
71 uses HT_CHAIN_END_UNITID_BASE
72 uses SB_HT_CHAIN_ON_BUS0
73 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
75 uses CONFIG_LB_MEM_TOPK
78 ## ROM_SIZE is the size of boot ROM that this board will use.
80 default ROM_SIZE=524288
83 #default ROM_SIZE=1048576
87 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
89 #default FALLBACK_SIZE=131072
91 default FALLBACK_SIZE=0x40000
98 ## Build code for the fallback boot
100 default HAVE_FALLBACK_BOOT=1
103 ## Build code to reset the motherboard from linuxBIOS
105 default HAVE_HARD_RESET=1
108 ## Build code to export a programmable irq routing table
110 default HAVE_PIRQ_TABLE=1
111 default IRQ_SLOT_COUNT=11
114 ## Build code to export an x86 MP table
115 ## Useful for specifying IRQ routing values
117 default HAVE_MP_TABLE=1
120 ## Build code to export a CMOS option table
122 default HAVE_OPTION_TABLE=1
125 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
127 default LB_CKS_RANGE_START=49
128 default LB_CKS_RANGE_END=122
129 default LB_CKS_LOC=123
132 ## Build code for SMP support
133 ## Only worry about 2 micro processors
136 default CONFIG_MAX_CPUS=4
137 default CONFIG_MAX_PHYSICAL_CPUS=2
138 default CONFIG_LOGICAL_CPUS=1
141 default HW_MEM_HOLE_SIZEK=0x100000
143 ##HT Unit ID offset, default is 1, the typical one
144 default HT_CHAIN_UNITID_BASE=0x0
146 ##real SB Unit ID, default is 0x20, mean dont touch it at last
147 #default HT_CHAIN_END_UNITID_BASE=0x0
149 #make the SB HT chain on bus 0, default is not (0)
150 default SB_HT_CHAIN_ON_BUS0=2
152 ##only offset for SB chain?, default is yes(1)
153 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
156 #default CONFIG_CONSOLE_BTEXT=1
159 default CONFIG_CONSOLE_VGA=1
160 default CONFIG_PCI_ROM_RUN=1
163 ## enable CACHE_AS_RAM specifics
165 default USE_DCACHE_RAM=1
166 default DCACHE_RAM_BASE=0xcf000
167 default DCACHE_RAM_SIZE=0x1000
168 default CONFIG_USE_INIT=0
170 default ENABLE_APIC_EXT_ID=0
171 default APIC_ID_OFFSET=0x10
172 default LIFT_BSP_APIC_ID=0
175 #default CONFIG_PCI_64BIT_PREF_MEM=1
178 ## Build code to setup a generic IOAPIC
180 default CONFIG_IOAPIC=1
183 ## Clean up the motherboard id strings
185 default MAINBOARD_PART_NUMBER="s2891"
186 default MAINBOARD_VENDOR="Tyan"
187 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
188 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891
191 ### LinuxBIOS layout values
194 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
195 default ROM_IMAGE_SIZE = 65536
198 ## Use a small 8K stack
200 default STACK_SIZE=0x2000
203 ## Use a small 16K heap
205 default HEAP_SIZE=0x4000
208 ## Only use the option table in a normal image
210 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
213 ## LinuxBIOS C code runs at this location in RAM
215 default _RAMBASE=0x00004000
218 ## Load the payload from the ROM
220 default CONFIG_ROM_PAYLOAD = 1
223 ### Defaults of options that you may want to override in the target config file
227 ## The default compiler
229 default CC="$(CROSS_COMPILE)gcc-3.3.6 -m32"
230 default HOSTCC="gcc-3.3.6"
233 ## Disable the gdb stub by default
235 default CONFIG_GDB_STUB=0
238 ## The Serial Console
241 # To Enable the Serial Console
242 default CONFIG_CONSOLE_SERIAL8250=1
244 ## Select the serial console baud rate
245 default TTYS0_BAUD=115200
246 #default TTYS0_BAUD=57600
247 #default TTYS0_BAUD=38400
248 #default TTYS0_BAUD=19200
249 #default TTYS0_BAUD=9600
250 #default TTYS0_BAUD=4800
251 #default TTYS0_BAUD=2400
252 #default TTYS0_BAUD=1200
254 # Select the serial console base port
255 default TTYS0_BASE=0x3f8
257 # Select the serial protocol
258 # This defaults to 8 data bits, 1 stop bit, and no parity
259 default TTYS0_LCS=0x3
262 ### Select the linuxBIOS loglevel
264 ## EMERG 1 system is unusable
265 ## ALERT 2 action must be taken immediately
266 ## CRIT 3 critical conditions
267 ## ERR 4 error conditions
268 ## WARNING 5 warning conditions
269 ## NOTICE 6 normal but significant condition
270 ## INFO 7 informational
271 ## DEBUG 8 debug-level messages
272 ## SPEW 9 Way too many details
274 ## Request this level of debugging output
275 default DEFAULT_CONSOLE_LOGLEVEL=8
276 ## At a maximum only compile in this level of debugging
277 default MAXIMUM_CONSOLE_LOGLEVEL=8
280 ## Select power on after power fail setting
281 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"