1 include /config/nofailovercalculation.lb
2 default CONFIG_ROM_PAYLOAD = 1
7 ## Build the objects we have code for in this directory.
12 #dir /drivers/ati/ragexl
14 #needed by irq_tables and mptable and acpi_tables
17 if HAVE_MP_TABLE object mptable.o end
18 if HAVE_PIRQ_TABLE object irq_tables.o end
24 depends "$(MAINBOARD)/dsdt.dsl"
25 action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
26 action "mv dsdt.hex dsdt.c"
29 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
30 #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
35 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
36 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
40 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
41 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
42 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
43 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
48 ## Build our 16 bit and 32 bit coreboot entry code
51 mainboardinit cpu/x86/16bit/entry16.inc
52 ldscript /cpu/x86/16bit/entry16.lds
55 mainboardinit cpu/x86/32bit/entry32.inc
58 ldscript /cpu/x86/32bit/entry32.lds
62 ldscript /cpu/amd/car/cache_as_ram.lds
66 ## Build our reset vector (This is where coreboot is entered)
69 mainboardinit cpu/x86/16bit/reset16.inc
70 ldscript /cpu/x86/16bit/reset16.lds
72 mainboardinit cpu/x86/32bit/reset32.inc
73 ldscript /cpu/x86/32bit/reset32.lds
77 ## Include an id string (For safe flashing)
79 mainboardinit southbridge/nvidia/ck804/id.inc
80 ldscript /southbridge/nvidia/ck804/id.lds
83 ## ROMSTRAP table for CK804
86 mainboardinit southbridge/nvidia/ck804/romstrap.inc
87 ldscript /southbridge/nvidia/ck804/romstrap.lds
93 mainboardinit cpu/amd/car/cache_as_ram.inc
96 ### This is the early phase of coreboot startup
97 ### Things are delicate and we test to see if we should
98 ### failover to another image.
100 if USE_FALLBACK_IMAGE
101 ldscript /arch/i386/lib/failover.lds
105 ### O.k. We aren't just an intermediary anymore!
114 mainboardinit ./auto.inc
118 ## Include the secondary Configuration files
122 # sample config for tyan/s2891
123 chip northbridge/amd/amdk8/root_complex
124 device apic_cluster 0 on
125 chip cpu/amd/socket_940
129 device pci_domain 0 on
130 chip northbridge/amd/amdk8 #mc0
131 device pci 18.0 on # northbridge
132 # devices on link 0, link 0 == LDT 0
133 chip southbridge/nvidia/ck804
134 device pci 0.0 on end # HT
135 device pci 1.0 on # LPC
136 chip superio/winbond/w83627hf
137 device pnp 2e.0 off # Floppy
142 device pnp 2e.1 off # Parallel Port
146 device pnp 2e.2 on # Com1
150 device pnp 2e.3 off # Com2
154 device pnp 2e.5 on # Keyboard
160 device pnp 2e.6 off # CIR
163 device pnp 2e.7 off # GAME_MIDI_GIPO1
168 device pnp 2e.8 off end # GPIO2
169 device pnp 2e.9 off end # GPIO3
170 device pnp 2e.a off end # ACPI
171 device pnp 2e.b off # HW Monitor
177 device pci 1.1 on # SM 0
178 # chip drivers/generic/generic #dimm 0-0-0
179 # device i2c 50 on end
181 # chip drivers/generic/generic #dimm 0-0-1
182 # device i2c 51 on end
184 # chip drivers/generic/generic #dimm 0-1-0
185 # device i2c 52 on end
187 # chip drivers/generic/generic #dimm 0-1-1
188 # device i2c 53 on end
190 # chip drivers/generic/generic #dimm 1-0-0
191 # device i2c 54 on end
193 # chip drivers/generic/generic #dimm 1-0-1
194 # device i2c 55 on end
196 # chip drivers/generic/generic #dimm 1-1-0
197 # device i2c 56 on end
199 # chip drivers/generic/generic #dimm 1-1-1
200 # device i2c 57 on end
203 # device pci 1.1 on # SM 1
204 # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
205 # device i2c 2d on end
207 # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
208 # device i2c 2e on end
210 # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
211 # device i2c 2a on end
213 # chip drivers/generic/generic # Winbond HWM 0x92
214 # device i2c 49 on end
216 # chip drivers/generic/generic # Winbond HWM 0x94
217 # device i2c 4a on end
220 device pci 2.0 on end # USB 1.1
221 device pci 2.1 on end # USB 2
222 device pci 4.0 off end # ACI
223 device pci 4.1 off end # MCI
224 device pci 6.0 on end # IDE
225 device pci 7.0 on end # SATA 1
226 device pci 8.0 on end # SATA 0
227 device pci 9.0 on # PCI
228 # chip drivers/ati/ragexl
229 chip drivers/pci/onboard
230 device pci 7.0 on end
231 #register "rom_address" = "0xfff80000" #for 512K
232 register "rom_address" = "0xfff00000" #for 1M
235 device pci a.0 off end # NIC
236 device pci b.0 off end # PCI E 3
237 device pci c.0 off end # PCI E 2
238 device pci d.0 on end # PCI E 1
239 device pci e.0 on end # PCI E 0
240 register "ide0_enable" = "1"
241 register "ide1_enable" = "1"
242 register "sata0_enable" = "1"
243 register "sata1_enable" = "1"
245 end # device pci 18.0
246 device pci 18.0 on end # Link 1
248 # devices on link 2, link 2 == LDT 2
249 chip southbridge/amd/amd8131
250 # the on/off keyword is mandatory
251 device pci 0.0 on end
252 device pci 0.1 on end
254 chip drivers/pci/onboard
255 device pci 9.0 on end
256 device pci 9.1 on end
259 device pci 1.1 on end
261 end # device pci 18.0
262 device pci 18.1 on end
263 device pci 18.2 on end
264 device pci 18.3 on end
269 # chip drivers/generic/debug
270 # device pnp 0.0 off end # chip name
271 # device pnp 0.1 off end # pci_regs_all
272 # device pnp 0.2 off end # mem
273 # device pnp 0.3 off end # cpuid
274 # device pnp 0.4 off end # smbus_regs_all
275 # device pnp 0.5 off end # dual core msr
276 # device pnp 0.6 off end # cache size
277 # device pnp 0.7 off end # tsc
278 # device pnp 0.8 on end # hard_reset