src/mainboard/tyan/s2891/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE         = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19 default CONFIG_ROM_PAYLOAD       = 1
  20
  21 ##
  22 ## Compute where this copy of coreboot will start in the boot rom
  23 ##
  24 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  25
  26 ##
  27 ## Compute a range of ROM that can cached to speed up coreboot,
  28 ## execution speed.
  29 ##
  30 ## XIP_ROM_SIZE must be a power of 2.
  31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  32 ##
  33 default XIP_ROM_SIZE=65536
  34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  35
  36 arch i386 end
  37
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44
  45 #dir /drivers/ati/ragexl
  46
  47 #needed by irq_tables and mptable and acpi_tables
  48 object get_bus_conf.o
  49
  50 if HAVE_MP_TABLE object mptable.o end
  51 if HAVE_PIRQ_TABLE object irq_tables.o end
  52 #object reset.o
  53
  54 if USE_DCACHE_RAM
  55
  56 if CONFIG_USE_INIT
  57         makerule ./auto.o
  58                 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  59                 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  60         end
  61 else
  62         makerule ./auto.inc
  63                 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  64                 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  65                 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  66                 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  67         end
  68 end
  69
  70 else
  71         ##
  72         ## Romcc output
  73         ##
  74         makerule ./failover.E
  75                 depends "$(MAINBOARD)/failover.c ../romcc"
  76                 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  77         end
  78
  79         makerule ./failover.inc
  80                 depends "$(MAINBOARD)/failover.c ../romcc"
  81                 action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  82         end
  83
  84         makerule ./auto.E
  85                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  86                 action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  87         end
  88
  89         makerule ./auto.inc
  90                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  91                 action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  92         end
  93
  94 end
  95
  96 ##
  97 ## Build our 16 bit and 32 bit coreboot entry code
  98 ##
  99 if USE_FALLBACK_IMAGE
 100         mainboardinit cpu/x86/16bit/entry16.inc
 101         ldscript /cpu/x86/16bit/entry16.lds
 102 end
 103
 104 mainboardinit cpu/x86/32bit/entry32.inc
 105
 106 if USE_DCACHE_RAM
 107         if CONFIG_USE_INIT
 108                 ldscript /cpu/x86/32bit/entry32.lds
 109         end
 110
 111         if CONFIG_USE_INIT
 112                 ldscript /cpu/amd/car/cache_as_ram.lds
 113         end
 114 end
 115
 116 ##
 117 ## Build our reset vector (This is where coreboot is entered)
 118 ##
 119 if USE_FALLBACK_IMAGE
 120         mainboardinit cpu/x86/16bit/reset16.inc
 121         ldscript /cpu/x86/16bit/reset16.lds
 122 else
 123         mainboardinit cpu/x86/32bit/reset32.inc
 124         ldscript /cpu/x86/32bit/reset32.lds
 125 end
 126
 127 if USE_DCACHE_RAM
 128 else
 129         ### Should this be in the northbridge code?
 130         mainboardinit arch/i386/lib/cpu_reset.inc
 131 end
 132
 133 ##
 134 ## Include an id string (For safe flashing)
 135 ##
 136 mainboardinit southbridge/nvidia/ck804/id.inc
 137 ldscript /southbridge/nvidia/ck804/id.lds
 138
 139 ##
 140 ## ROMSTRAP table for CK804
 141 ##
 142 if USE_FALLBACK_IMAGE
 143         mainboardinit southbridge/nvidia/ck804/romstrap.inc
 144         ldscript /southbridge/nvidia/ck804/romstrap.lds
 145 end
 146
 147 if USE_DCACHE_RAM
 148         ##
 149         ## Setup Cache-As-Ram
 150         ##
 151         mainboardinit cpu/amd/car/cache_as_ram.inc
 152 end
 153
 154 ###
 155 ### This is the early phase of coreboot startup
 156 ### Things are delicate and we test to see if we should
 157 ### failover to another image.
 158 ###
 159 if USE_FALLBACK_IMAGE
 160         ldscript /arch/i386/lib/failover.lds
 161         if USE_DCACHE_RAM
 162         else
 163                 mainboardinit ./failover.inc
 164         end
 165 end
 166
 167 ###
 168 ### O.k. We aren't just an intermediary anymore!
 169 ###
 170
 171 ##
 172 ## Setup RAM
 173 ##
 174 if USE_DCACHE_RAM
 175
 176         if CONFIG_USE_INIT
 177                 initobject auto.o
 178         else
 179                 mainboardinit ./auto.inc
 180         end
 181
 182 else
 183         # ROMCC
 184         mainboardinit cpu/x86/fpu/enable_fpu.inc
 185         mainboardinit cpu/x86/mmx/enable_mmx.inc
 186         mainboardinit cpu/x86/sse/enable_sse.inc
 187         mainboardinit ./auto.inc
 188         mainboardinit cpu/x86/sse/disable_sse.inc
 189         mainboardinit cpu/x86/mmx/disable_mmx.inc
 190
 191 end
 192
 193 ##
 194 ## Include the secondary Configuration files
 195 ##
 196 if CONFIG_CHIP_NAME
 197         config chip.h
 198 end
 199
 200 # sample config for tyan/s2891
 201 chip northbridge/amd/amdk8/root_complex
 202         device apic_cluster 0 on
 203                 chip cpu/amd/socket_940
 204                         device apic 0 on end
 205                 end
 206         end
 207         device pci_domain 0 on
 208                 chip northbridge/amd/amdk8 #mc0
 209                         device pci 18.0 on #  northbridge
 210                                 #  devices on link 0, link 0 == LDT 0
 211                                 chip southbridge/nvidia/ck804
 212                                         device pci 0.0 on end   # HT
 213                                         device pci 1.0 on # LPC
 214                                                 chip superio/winbond/w83627hf
 215                                                         device pnp 2e.0 off #  Floppy
 216                                                                 io 0x60 = 0x3f0
 217                                                                 irq 0x70 = 6
 218                                                                 drq 0x74 = 2
 219                                                         end
 220                                                         device pnp 2e.1 off #  Parallel Port
 221                                                                 io 0x60 = 0x378
 222                                                                 irq 0x70 = 7
 223                                                         end
 224                                                         device pnp 2e.2 on #  Com1
 225                                                                 io 0x60 = 0x3f8
 226                                                                 irq 0x70 = 4
 227                                                         end
 228                                                         device pnp 2e.3 off #  Com2
 229                                                                 io 0x60 = 0x2f8
 230                                                                 irq 0x70 = 3
 231                                                         end
 232                                                         device pnp 2e.5 on #  Keyboard
 233                                                                 io 0x60 = 0x60
 234                                                                 io 0x62 = 0x64
 235                                                                 irq 0x70 = 1
 236                                                                 irq 0x72 = 12
 237                                                         end
 238                                                         device pnp 2e.6 off #  CIR
 239                                                                 io 0x60 = 0x100
 240                                                         end
 241                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 242                                                                 io 0x60 = 0x220
 243                                                                 io 0x62 = 0x300
 244                                                                 irq 0x70 = 9
 245                                                         end
 246                                                         device pnp 2e.8 off end #  GPIO2
 247                                                         device pnp 2e.9 off end #  GPIO3
 248                                                         device pnp 2e.a off end #  ACPI
 249                                                         device pnp 2e.b off #  HW Monitor
 250                                                                 io 0x60 = 0x290
 251                                                                 irq 0x70 = 5
 252                                                         end
 253                                                 end
 254                                         end
 255                                         device pci 1.1 on # SM 0
 256 #                                               chip drivers/generic/generic #dimm 0-0-0
 257 #                                                       device i2c 50 on end
 258 #                                               end
 259 #                                               chip drivers/generic/generic #dimm 0-0-1
 260 #                                                       device i2c 51 on end
 261 #                                               end
 262 #                                               chip drivers/generic/generic #dimm 0-1-0
 263 #                                                       device i2c 52 on end
 264 #                                               end
 265 #                                               chip drivers/generic/generic #dimm 0-1-1
 266 #                                                       device i2c 53 on end
 267 #                                               end
 268 #                                               chip drivers/generic/generic #dimm 1-0-0
 269 #                                                       device i2c 54 on end
 270 #                                               end
 271 #                                               chip drivers/generic/generic #dimm 1-0-1
 272 #                                                       device i2c 55 on end
 273 #                                               end
 274 #                                               chip drivers/generic/generic #dimm 1-1-0
 275 #                                                       device i2c 56 on end
 276 #                                               end
 277 #                                               chip drivers/generic/generic #dimm 1-1-1
 278 #                                                       device i2c 57 on end
 279 #                                               end
 280                                         end # SM
 281 #                                       device pci 1.1 on # SM 1
 282 #                                               chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
 283 #                                                       device i2c 2d on end
 284 #                                               end
 285 #                                               chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
 286 #                                                       device i2c 2e on end
 287 #                                               end
 288 #                                               chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
 289 #                                                       device i2c 2a on end
 290 #                                               end
 291 #                                               chip drivers/generic/generic # Winbond HWM 0x92
 292 #                                                       device i2c 49 on end
 293 #                                               end
 294 #                                               chip drivers/generic/generic # Winbond HWM 0x94
 295 #                                                       device i2c 4a on end
 296 #                                               end
 297 #                                       end #SM
 298                                         device pci 2.0 on end # USB 1.1
 299                                         device pci 2.1 on end # USB 2
 300                                         device pci 4.0 off end # ACI
 301                                         device pci 4.1 off end # MCI
 302                                         device pci 6.0 on end # IDE
 303                                         device pci 7.0 on end # SATA 1
 304                                         device pci 8.0 on end # SATA 0
 305                                         device pci 9.0 on  # PCI
 306                                         #       chip drivers/ati/ragexl
 307                                                 chip drivers/pci/onboard
 308                                                         device pci 7.0 on end
 309                                                         #register "rom_address" = "0xfff80000" #for 512K
 310                                                         register "rom_address" = "0xfff00000" #for 1M
 311                                                 end
 312                                         end
 313                                         device pci a.0 off end # NIC
 314                                         device pci b.0 off end # PCI E 3
 315                                         device pci c.0 off end # PCI E 2
 316                                         device pci d.0 on end # PCI E 1
 317                                         device pci e.0 on end # PCI E 0
 318                                         register "ide0_enable" = "1"
 319                                         register "ide1_enable" = "1"
 320                                         register "sata0_enable" = "1"
 321                                         register "sata1_enable" = "1"
 322                                 end
 323                         end #  device pci 18.0
 324                         device pci 18.0 on end # Link 1
 325                         device pci 18.0 on
 326                         #  devices on link 2, link 2 == LDT 2
 327                                 chip southbridge/amd/amd8131
 328                                         # the on/off keyword is mandatory
 329                                         device pci 0.0 on end
 330                                         device pci 0.1 on end
 331                                         device pci 1.0 on
 332                                                 chip drivers/pci/onboard
 333                                                         device pci 9.0 on end
 334                                                         device pci 9.1 on end
 335                                                 end
 336                                         end
 337                                         device pci 1.1 on end
 338                                 end
 339                         end # device pci 18.0
 340                         device pci 18.1 on end
 341                         device pci 18.2 on end
 342                         device pci 18.3 on end
 343                 end #mc0
 344
 345         end # pci_domain
 346
 347 #       chip drivers/generic/debug
 348 #               device pnp 0.0 off end # chip name
 349 #               device pnp 0.1 off end # pci_regs_all
 350 #               device pnp 0.2 off end # mem
 351 #               device pnp 0.3 off end # cpuid
 352 #               device pnp 0.4 off end # smbus_regs_all
 353 #               device pnp 0.5 off end # dual core msr
 354 #               device pnp 0.6 off end # cache size
 355 #               device pnp 0.7 off end # tsc
 356 #               device pnp 0.8 on  end # hard_reset
 357 #       end
 358 end # root_complex