src/mainboard/tyan/s2885/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <pc80/mc146818rtc.h>
   8 #include <console/console.h>
   9 #include <lib.h>
  10 #include <spd.h>
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/amd/amd8111/early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "northbridge/amd/amdk8/debug.c"
  19 #include "superio/winbond/w83627hf/early_serial.c"
  20 #include "cpu/x86/mtrr/earlymtrr.c"
  21 #include "cpu/x86/bist.h"
  22 #include "northbridge/amd/amdk8/setup_resource_map.c"
  23 #include "southbridge/amd/amd8111/early_ctrl.c"
  24
  25 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  26
  27 static void memreset_setup(void)
  28 {
  29    if (is_cpu_pre_c0())
  30         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  31    else
  32         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  33    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  34 }
  35
  36 static void memreset(int controllers, const struct mem_controller *ctrl)
  37 {
  38    if (is_cpu_pre_c0()) {
  39         udelay(800);
  40         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  41         udelay(90);
  42    }
  43 }
  44
  45 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  46
  47 static inline int spd_read_byte(unsigned device, unsigned address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 #include "northbridge/amd/amdk8/raminit.c"
  53 #include "northbridge/amd/amdk8/coherent_ht.c"
  54 #include "lib/generic_sdram.c"
  55 #include "resourcemap.c"
  56 #include "cpu/amd/dualcore/dualcore.c"
  57 #include "cpu/amd/car/post_cache_as_ram.c"
  58 #include "cpu/amd/model_fxx/init_cpus.c"
  59
  60 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  61 {
  62         static const uint16_t spd_addr [] = {
  63                         DIMM0, DIMM2, 0, 0,
  64                         DIMM1, DIMM3, 0, 0,
  65 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  66                         DIMM4, DIMM6, 0, 0,
  67                         DIMM5, DIMM7, 0, 0,
  68 #endif
  69         };
  70
  71         int needs_reset;
  72         unsigned bsp_apicid = 0, nodes;
  73         struct mem_controller ctrl[8];
  74
  75         if (bist == 0)
  76                 bsp_apicid = init_cpus(cpu_init_detectedx);
  77
  78         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  79         console_init();
  80
  81 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
  82
  83         /* Halt if there was a built in self test failure */
  84         report_bist_failure(bist);
  85
  86         setup_s2885_resource_map();
  87 #if 0
  88         dump_pci_device(PCI_DEV(0, 0x18, 0));
  89         dump_pci_device(PCI_DEV(0, 0x19, 0));
  90 #endif
  91
  92         needs_reset = setup_coherent_ht_domain();
  93
  94         wait_all_core0_started();
  95 #if CONFIG_LOGICAL_CPUS==1
  96         // It is said that we should start core1 after all core0 launched
  97         start_other_cores();
  98         wait_all_other_cores_started(bsp_apicid);
  99 #endif
 100
 101         needs_reset |= ht_setup_chains_x();
 102
 103         if (needs_reset) {
 104                 print_info("ht reset -\n");
 105                 soft_reset();
 106         }
 107
 108         allow_all_aps_stop(bsp_apicid);
 109
 110         nodes = get_nodes();
 111         //It's the time to set ctrl now;
 112         fill_mem_ctrl(nodes, ctrl, spd_addr);
 113
 114         enable_smbus();
 115
 116         memreset_setup();
 117         sdram_initialize(nodes, ctrl);
 118
 119 #if 0
 120         dump_pci_devices();
 121 #endif
 122
 123         post_cache_as_ram();
 124 }