1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 void *smp_write_config_table(void *v, unsigned long * processor_map)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "TYAN ";
11 static const char productid[12] = "S2885 ";
12 struct mp_config_table *mc;
14 unsigned char bus_num;
15 unsigned char bus_isa;
16 unsigned char bus_8111_0;
17 unsigned char bus_8111_1;
18 unsigned char bus_8131_1;
19 unsigned char bus_8131_2;
20 unsigned char bus_8151_1;
22 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
23 memset(mc, 0, sizeof(*mc));
25 memcpy(mc->mpc_signature, sig, sizeof(sig));
26 mc->mpc_length = sizeof(*mc); /* initially just the header */
28 mc->mpc_checksum = 0; /* not yet computed */
29 memcpy(mc->mpc_oem, oem, sizeof(oem));
30 memcpy(mc->mpc_productid, productid, sizeof(productid));
33 mc->mpc_entry_count = 0; /* No entries yet... */
34 mc->mpc_lapic = LAPIC_ADDR;
39 smp_write_processors(mc, processor_map);
45 dev = dev_find_slot(3, PCI_DEVFN(0x03,0));
47 bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
48 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
49 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
51 printk_debug("bus_isa=%d\n",bus_isa);
53 printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n");
59 dev = dev_find_slot(3, PCI_DEVFN(0x01,0));
61 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
63 printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n");
67 dev = dev_find_slot(3, PCI_DEVFN(0x02,0));
69 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
71 printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n");
75 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
77 bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
78 printk_debug("bus_8151_1=%d\n",bus_8151_1);
80 printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
86 /* define bus and isa numbers */
87 for (bus_num = 0; bus_num < bus_isa; bus_num++) {
88 smp_write_bus(mc, bus_num, "PCI ");
90 smp_write_bus(mc, bus_isa, "ISA ");
92 /*I/O APICs: APIC ID Version State Address*/
93 smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
98 dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
100 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
101 base &= PCI_BASE_ADDRESS_MEM_MASK;
102 smp_write_ioapic(mc, 3, 0x11, base);
105 dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
107 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
108 base &= PCI_BASE_ADDRESS_MEM_MASK;
109 smp_write_ioapic(mc, 4, 0x11, base);
113 /* ISA Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
114 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
128 /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
129 // Integrated SMBus 2.0
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
131 // Integrated AMD AC97 Audio
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
134 // Integrated AMD USB
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
137 // Onboard Serial ATA
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
142 // Onboard Broadcom NIC
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x09<<2)|0, 0x3, 0x0);
145 // AGP Display Adapter
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|0, 0x3, 0x3);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|1, 0x3, 0x0);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|2, 0x3, 0x1);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|3, 0x3, 0x2);
161 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|0, 0x3, 0x2);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|1, 0x3, 0x3);
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|2, 0x3, 0x0);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|3, 0x3, 0x1);
166 //Slot 1 PCI-X 133/100/66
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|0, 0x4, 0x0);
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|1, 0x4, 0x1);
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|2, 0x4, 0x2);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|3, 0x4, 0x3);
172 //Slot 2 PCI-X 133/100/66
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|0, 0x4, 0x1);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|1, 0x4, 0x2);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|2, 0x4, 0x3);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|3, 0x4, 0x0);
178 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
179 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
180 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
182 /* There is no extension information... */
184 /* Compute the checksums */
185 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
186 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
187 printk_debug("Wrote the mp table end at: %p - %p\n",
188 mc, smp_next_mpe_entry(mc));
189 return smp_next_mpe_entry(mc);
192 unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
195 v = smp_write_floating_table(addr);
196 return (unsigned long)smp_write_config_table(v, processor_map);