4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
15 #include "northbridge/amd/amdk8/incoherent_ht.c"
16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
17 #include "northbridge/amd/amdk8/raminit.h"
18 #include "cpu/amd/model_fxx/apic_timer.c"
19 #include "lib/delay.c"
20 #include "cpu/x86/lapic/boot_cpu.c"
21 #include "northbridge/amd/amdk8/reset_test.c"
22 #include "northbridge/amd/amdk8/debug.c"
23 #include "northbridge/amd/amdk8/cpu_rev.c"
24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
26 #include "cpu/x86/bist.h"
28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
30 static void hard_reset(void)
35 pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
40 static void soft_reset(void)
43 pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
45 static void soft2_reset(void)
48 pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
51 static void memreset_setup(void)
54 if (is_cpu_pre_c0()) {
55 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
59 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
63 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
66 static void memreset(int controllers, const struct mem_controller *ctrl)
69 if (is_cpu_pre_c0()) {
71 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
77 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
79 /* Routing Table Node i
81 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
82 * i: 0, 1, 2, 3, 4, 5, 6, 7
84 * [ 0: 3] Request Route
85 * [0] Route to this node
89 * [11: 8] Response Route
90 * [0] Route to this node
94 * [19:16] Broadcast route
95 * [0] Route to this node
101 uint32_t ret=0x00010101; /* default row entry */
104 CPU1-------------CPU0--------8131------8111
113 /* Link1 of CPU0 to Link1 of CPU1 */
114 static const unsigned int rows_2p[2][2] = {
115 { 0x00050101, 0x00010404 },
116 { 0x00010404, 0x00050101 }
120 // print_debug("this mainboard is only designed for 2 cpus\r\n");
125 if (!(node>=maxnodes || row>=maxnodes)) {
126 ret=rows_2p[node][row];
132 static inline void activate_spd_rom(const struct mem_controller *ctrl)
137 static inline int spd_read_byte(unsigned device, unsigned address)
139 return smbus_read_byte(device, address);
142 //#include "northbridge/amd/amdk8/setup_resource_map.c"
143 #include "northbridge/amd/amdk8/raminit.c"
144 #include "northbridge/amd/amdk8/coherent_ht.c"
145 #include "sdram/generic_sdram.c"
147 #include "resourcemap.c" /* tyan does not want the default */
151 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
152 static void main(unsigned long bist)
154 static const struct mem_controller cpu[] = {
158 .f0 = PCI_DEV(0, 0x18, 0),
159 .f1 = PCI_DEV(0, 0x18, 1),
160 .f2 = PCI_DEV(0, 0x18, 2),
161 .f3 = PCI_DEV(0, 0x18, 3),
162 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
163 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
169 .f0 = PCI_DEV(0, 0x19, 0),
170 .f1 = PCI_DEV(0, 0x19, 1),
171 .f2 = PCI_DEV(0, 0x19, 2),
172 .f3 = PCI_DEV(0, 0x19, 3),
173 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
174 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
180 static const struct ht_chain ht_c[] = {
181 { /* Link 2 of CPU0 */
182 .udev = PCI_DEV(0, 0x18, 0),
184 .devreg = 0xe0, /* Preset bus num in resource map */
186 { /* Link 0 of CPU0 */
187 .udev = PCI_DEV(0, 0x18, 0),
189 .devreg = 0xe4, /* Preset bus num in resource map */
196 /* Skip this if there was a built in self test failure */
197 amd_early_mtrr_init();
201 if (cpu_init_detected()) {
203 asm volatile ("jmp __cpu_reset");
205 /* cpu reset also reset the memtroller ????
206 need soft_reset to reset all except keep HT link freq and width */
207 distinguish_cpu_resets();
211 distinguish_cpu_resets();
217 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
221 /* Halt if there was a built in self test failure */
222 // report_bist_failure(bist);
224 setup_s2885_resource_map();
225 needs_reset = setup_coherent_ht_domain();
227 needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
229 needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
232 print_info("ht reset -\r\n");
238 dump_spd_registers(&cpu[0]);
241 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
247 dump_pci_device(PCI_DEV(0, 0x18, 1));
249 /* Check all of memory */
252 msr = rdmsr(TOP_MEM2);
253 print_debug("TOP_MEM2: ");
254 print_debug_hex32(msr.hi);
255 print_debug_hex32(msr.lo);
258 ram_check(0x00000000, msr.lo+(msr.hi<<32));
265 // Check 16MB of memory @ 0
266 ram_check(0x00000000, 0x00100000);
268 // Check 16MB of memory @ 2GB
269 // ram_check(0x80000000, 0x80100000);