src/mainboard/tyan/s2885/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/smp/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/k8/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/p6/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "debug.c"
  22 #include "northbridge/amd/amdk8/cpu_rev.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  26
  27 static void hard_reset(void)
  28 {
  29         set_bios_reset();
  30
  31         /* enable cf9 */
  32         pci_write_config8(PCI_DEV(1, 0x04, 3), 0x41, 0xf1);
  33         /* reset */
  34         outb(0x0e, 0x0cf9);
  35 }
  36
  37 static void soft_reset(void)
  38 {
  39         set_bios_reset();
  40         pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
  41 }
  42
  43 #define REV_B_RESET 0
  44 static void memreset_setup(void)
  45 {
  46 #if REV_B_RESET==1
  47         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  48 #else
  49         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  50 #endif
  51         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56         udelay(800);
  57 #if REV_B_RESET==1
  58         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  59 #endif
  60         udelay(90);
  61 }
  62
  63 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  64 {
  65         /* Routing Table Node i
  66          *
  67          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  68          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  69          *
  70          * [ 0: 3] Request Route
  71          *     [0] Route to this node
  72          *     [1] Route to Link 0
  73          *     [2] Route to Link 1
  74          *     [3] Route to Link 2
  75          * [11: 8] Response Route
  76          *     [0] Route to this node
  77          *     [1] Route to Link 0
  78          *     [2] Route to Link 1
  79          *     [3] Route to Link 2
  80          * [19:16] Broadcast route
  81          *     [0] Route to this node
  82          *     [1] Route to Link 0
  83          *     [2] Route to Link 1
  84          *     [3] Route to Link 2
  85          */
  86
  87         uint32_t ret=0x00010101; /* default row entry */
  88
  89         static const unsigned int rows_2p[2][2] = {
  90                 { 0x00050101, 0x00010404 },
  91                 { 0x00010404, 0x00050101 }
  92         };
  93
  94         if(maxnodes>2) {
  95                 print_debug("this mainboard is only designed for 2 cpus\r\n");
  96                 maxnodes=2;
  97         }
  98
  99
 100         if (!(node>=maxnodes || row>=maxnodes)) {
 101                 ret=rows_2p[node][row];
 102         }
 103
 104         return ret;
 105 }
 106
 107 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 108 {
 109         /* nothing to do */
 110 }
 111
 112 static inline int spd_read_byte(unsigned device, unsigned address)
 113 {
 114         return smbus_read_byte(device, address);
 115 }
 116
 117 /* include mainboard specific ht code */
 118 #include "hypertransport.c"
 119
 120 #include "northbridge/amd/amdk8/raminit.c"
 121 #include "northbridge/amd/amdk8/coherent_ht.c"
 122 #include "sdram/generic_sdram.c"
 123
 124 #include "resourcemap.c" /* tyan does not want the default */
 125
 126 #define FIRST_CPU  1
 127 #define SECOND_CPU 1
 128 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 129 static void main(void)
 130 {
 131         static const struct mem_controller cpu[] = {
 132 #if FIRST_CPU
 133                 {
 134                         .node_id = 0,
 135                         .f0 = PCI_DEV(0, 0x18, 0),
 136                         .f1 = PCI_DEV(0, 0x18, 1),
 137                         .f2 = PCI_DEV(0, 0x18, 2),
 138                         .f3 = PCI_DEV(0, 0x18, 3),
 139                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 140                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 141                 },
 142 #endif
 143 #if SECOND_CPU
 144                 {
 145                         .node_id = 1,
 146                         .f0 = PCI_DEV(0, 0x19, 0),
 147                         .f1 = PCI_DEV(0, 0x19, 1),
 148                         .f2 = PCI_DEV(0, 0x19, 2),
 149                         .f3 = PCI_DEV(0, 0x19, 3),
 150                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 151                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 152                 },
 153 #endif
 154         };
 155         int needs_reset;
 156         enable_lapic();
 157         init_timer();
 158         if (cpu_init_detected()) {
 159                 asm("jmp __cpu_reset");
 160         }
 161         distinguish_cpu_resets();
 162         if (!boot_cpu()) {
 163                 stop_this_cpu();
 164         }
 165         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 166         uart_init();
 167         console_init();
 168         setup_s2885_resource_map();
 169         needs_reset = setup_coherent_ht_domain();
 170         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 171         if (needs_reset) {
 172                 print_info("ht reset -");
 173                 soft_reset();
 174         }
 175
 176 #if 0
 177         print_pci_devices();
 178 #endif
 179         enable_smbus();
 180 #if 0
 181         dump_spd_registers(&cpu[0]);
 182 #endif
 183         memreset_setup();
 184         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 185
 186 #if 0
 187         dump_pci_devices();
 188 #endif
 189 #if 0
 190         dump_pci_device(PCI_DEV(0, 0x18, 1));
 191 #endif
 192
 193         /* Check all of memory */
 194 #if 0
 195         msr_t msr;
 196         msr = rdmsr(TOP_MEM2);
 197         print_debug("TOP_MEM2: ");
 198         print_debug_hex32(msr.hi);
 199         print_debug_hex32(msr.lo);
 200         print_debug("\r\n");
 201 #endif
 202 /*
 203 #if  0
 204         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 205 #else
 206 #if TOTAL_CPUS < 2
 207         // Check 16MB of memory @ 0
 208         ram_check(0x00000000, 0x00100000);
 209 #else
 210         // Check 16MB of memory @ 2GB
 211         ram_check(0x80000000, 0x80100000);
 212 #endif
 213 #endif
 214 */
 215 }