src/mainboard/tyan/s2885/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 #define AMD8111_RESET PCI_DEV(     \
  47                 HARD_RESET_BUS,    \
  48                 HARD_RESET_DEVICE, \
  49                 HARD_RESET_FUNCTION)
  50
  51 static void soft2_reset(void)
  52 {
  53         set_bios_reset();
  54         pci_write_config8(AMD8111_RESET, 0x47, 1);
  55 }
  56
  57 static void memreset_setup(void)
  58 {
  59    if (is_cpu_pre_c0()) {
  60         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  61    }
  62    else {
  63         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  64    }
  65         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  66 }
  67
  68 static void memreset(int controllers, const struct mem_controller *ctrl)
  69 {
  70    if (is_cpu_pre_c0()) {
  71         udelay(800);
  72         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  73         udelay(90);
  74    }
  75 }
  76
  77 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  78 {
  79         /* Routing Table Node i
  80          *
  81          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  82          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  83          *
  84          * [ 0: 3] Request Route
  85          *     [0] Route to this node
  86          *     [1] Route to Link 0
  87          *     [2] Route to Link 1
  88          *     [3] Route to Link 2
  89          * [11: 8] Response Route
  90          *     [0] Route to this node
  91          *     [1] Route to Link 0
  92          *     [2] Route to Link 1
  93          *     [3] Route to Link 2
  94          * [19:16] Broadcast route
  95          *     [0] Route to this node
  96          *     [1] Route to Link 0
  97          *     [2] Route to Link 1
  98          *     [3] Route to Link 2
  99          */
 100
 101         uint32_t ret=0x00010101; /* default row entry */
 102 /*
 103             (L1)       (L1)  (L2)
 104         CPU1-------------CPU0--------8131------8111
 105                           |(L0)
 106                           |
 107                           |
 108                           |
 109                           |
 110                           |
 111                         8151
 112 */
 113         /* Link1 of CPU0 to Link1 of CPU1 */
 114         static const unsigned int rows_2p[2][2] = {
 115                 { 0x00050101, 0x00010404 },
 116                 { 0x00010404, 0x00050101 }
 117         };
 118
 119         if(maxnodes>2) {
 120                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 121                 maxnodes=2;
 122         }
 123
 124
 125         if (!(node>=maxnodes || row>=maxnodes)) {
 126                 ret=rows_2p[node][row];
 127         }
 128
 129         return ret;
 130 }
 131
 132 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 133 {
 134         /* nothing to do */
 135 }
 136
 137 static inline int spd_read_byte(unsigned device, unsigned address)
 138 {
 139         return smbus_read_byte(device, address);
 140 }
 141
 142 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 143 #include "northbridge/amd/amdk8/raminit.c"
 144 #include "northbridge/amd/amdk8/coherent_ht.c"
 145 #include "sdram/generic_sdram.c"
 146
 147 /* tyan does not want the default */
 148 #include "resourcemap.c"
 149
 150 #define FIRST_CPU  1
 151 #define SECOND_CPU 1
 152 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 153 static void main(unsigned long bist)
 154 {
 155         static const struct mem_controller cpu[] = {
 156 #if FIRST_CPU
 157                 {
 158                         .node_id = 0,
 159                         .f0 = PCI_DEV(0, 0x18, 0),
 160                         .f1 = PCI_DEV(0, 0x18, 1),
 161                         .f2 = PCI_DEV(0, 0x18, 2),
 162                         .f3 = PCI_DEV(0, 0x18, 3),
 163                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 164                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 165                 },
 166 #endif
 167 #if SECOND_CPU
 168                 {
 169                         .node_id = 1,
 170                         .f0 = PCI_DEV(0, 0x19, 0),
 171                         .f1 = PCI_DEV(0, 0x19, 1),
 172                         .f2 = PCI_DEV(0, 0x19, 2),
 173                         .f3 = PCI_DEV(0, 0x19, 3),
 174                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 175                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 176                 },
 177 #endif
 178         };
 179
 180 #if 1
 181         static const struct ht_chain ht_c[] = {
 182                 { /* Link 2 of CPU0 */
 183                         .udev = PCI_DEV(0, 0x18, 0),
 184                         .upos = 0xc0,
 185                         .devreg = 0xe0,  /* Preset bus num in resource map */
 186                 },
 187                 { /* Link 0 of CPU0 */
 188                         .udev = PCI_DEV(0, 0x18, 0),
 189                         .upos = 0x80,
 190                         .devreg = 0xe4,  /* Preset bus num in resource map */
 191                 },
 192         };
 193 #endif
 194
 195         int needs_reset;
 196         if (bist == 0) {
 197                 /* Skip this if there was a built in self test failure */
 198                 amd_early_mtrr_init();
 199                 enable_lapic();
 200                 init_timer();
 201
 202                 if (cpu_init_detected()) {
 203 #if 1
 204                         asm volatile ("jmp __cpu_reset");
 205 #else
 206                 /* cpu reset also reset the memtroller ????
 207                         need soft_reset to reset all except keep HT link freq and width */
 208                 /* So we don't need to
 209                         1. jmp to __cpu_reset
 210                         2. jmp to __main to copy ROM to ram (It costs some time)
 211                         3. call hardwaremain(), it will according to boot_complete to issue hard_reset in southbridge.
 212                                 (Actually it is soft2_reset(); --- without call hard_reset, the memory is corrupted.
 213                   We will call soft2_reset directly to spare time in 1 and 2 and 3.2
 214                 */
 215                         distinguish_cpu_resets();
 216                         soft2_reset();
 217 #endif
 218                 }
 219                 distinguish_cpu_resets();
 220                 if (!boot_cpu()) {
 221                         stop_this_cpu();
 222                 }
 223         }
 224
 225         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 226         uart_init();
 227         console_init();
 228
 229         /* Halt if there was a built in self test failure */
 230 //      report_bist_failure(bist);
 231
 232         setup_s2885_resource_map();
 233         needs_reset = setup_coherent_ht_domain();
 234 #if 0
 235         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
 236 #else
 237         needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
 238 #endif
 239         if (needs_reset) {
 240                 print_info("ht reset -\r\n");
 241                 soft_reset();
 242         }
 243
 244         enable_smbus();
 245 #if 0
 246         dump_spd_registers(&cpu[0]);
 247 #endif
 248         memreset_setup();
 249         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 250
 251 #if 0
 252         dump_pci_devices();
 253 #endif
 254 #if 0
 255         dump_pci_device(PCI_DEV(0, 0x18, 1));
 256 #endif
 257         /* Check all of memory */
 258 #if 0
 259         msr_t msr;
 260         msr = rdmsr(TOP_MEM2);
 261         print_debug("TOP_MEM2: ");
 262         print_debug_hex32(msr.hi);
 263         print_debug_hex32(msr.lo);
 264         print_debug("\r\n");
 265
 266         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 267
 268 #endif
 269
 270 #if 0
 271
 272 //#if TOTAL_CPUS < 2
 273         // Check 16MB of memory @ 0
 274         ram_check(0x00000000, 0x00100000);
 275 //#else
 276         // Check 16MB of memory @ 2GB
 277 //      ram_check(0x80000000, 0x80100000);
 278 //#endif
 279 #endif
 280
 281
 282 }