src/mainboard/tyan/s2885/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "northbridge/amd/amdk8/incoherent_ht.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26 #include "cpu/amd/dualcore/dualcore.c"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 /* Look up a which bus a given node/link combination is on.
  31  * return 0 when we can't find the answer.
  32  */
  33 static unsigned node_link_to_bus(unsigned node, unsigned link)
  34 {
  35         unsigned reg;
  36
  37         for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
  38                 unsigned config_map;
  39                 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
  40                 if ((config_map & 3) != 3) {
  41                         continue;
  42                 }
  43                 if ((((config_map >> 4) & 7) == node) &&
  44                         (((config_map >> 8) & 3) == link))
  45                 {
  46                         return (config_map >> 16) & 0xff;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 static void hard_reset(void)
  53 {
  54         device_t dev;
  55
  56         /* Find the device */
  57         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
  58
  59         set_bios_reset();
  60
  61         /* enable cf9 */
  62         pci_write_config8(dev, 0x41, 0xf1);
  63         /* reset */
  64         outb(0x0e, 0x0cf9);
  65 }
  66
  67 static void soft_reset(void)
  68 {
  69         device_t dev;
  70
  71         /* Find the device */
  72         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
  73
  74         set_bios_reset();
  75         pci_write_config8(dev, 0x47, 1);
  76 }
  77
  78 static void memreset_setup(void)
  79 {
  80    if (is_cpu_pre_c0()) {
  81         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  82    }
  83    else {
  84         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  85    }
  86         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  87 }
  88
  89 static void memreset(int controllers, const struct mem_controller *ctrl)
  90 {
  91    if (is_cpu_pre_c0()) {
  92         udelay(800);
  93         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  94         udelay(90);
  95    }
  96 }
  97
  98 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  99 {
 100         /* nothing to do */
 101 }
 102
 103 static inline int spd_read_byte(unsigned device, unsigned address)
 104 {
 105         return smbus_read_byte(device, address);
 106 }
 107
 108 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 109 #define QRANK_DIMM_SUPPORT 1
 110 #include "northbridge/amd/amdk8/raminit.c"
 111
 112 #if 0
 113         #define ENABLE_APIC_EXT_ID 1
 114         #define APIC_ID_OFFSET 0x10
 115         #define LIFT_BSP_APIC_ID 0
 116 #else
 117         #define ENABLE_APIC_EXT_ID 0
 118 #endif
 119 #include "northbridge/amd/amdk8/coherent_ht.c"
 120 #include "sdram/generic_sdram.c"
 121
 122 /* tyan does not want the default */
 123 #include "resourcemap.c"
 124
 125 #define FIRST_CPU  1
 126 #define SECOND_CPU 1
 127 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 128
 129 static void main(unsigned long bist)
 130 {
 131         static const struct mem_controller cpu[] = {
 132 #if FIRST_CPU
 133                 {
 134                         .node_id = 0,
 135                         .f0 = PCI_DEV(0, 0x18, 0),
 136                         .f1 = PCI_DEV(0, 0x18, 1),
 137                         .f2 = PCI_DEV(0, 0x18, 2),
 138                         .f3 = PCI_DEV(0, 0x18, 3),
 139                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 140                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 141                 },
 142 #endif
 143 #if SECOND_CPU
 144                 {
 145                         .node_id = 1,
 146                         .f0 = PCI_DEV(0, 0x19, 0),
 147                         .f1 = PCI_DEV(0, 0x19, 1),
 148                         .f2 = PCI_DEV(0, 0x19, 2),
 149                         .f3 = PCI_DEV(0, 0x19, 3),
 150                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 151                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 152                 },
 153 #endif
 154         };
 155
 156         int needs_reset;
 157
 158         if (bist == 0) {
 159                 k8_init_and_stop_secondaries();
 160         }
 161
 162         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 163         uart_init();
 164         console_init();
 165
 166         /* Halt if there was a built in self test failure */
 167         report_bist_failure(bist);
 168
 169         setup_s2885_resource_map();
 170         needs_reset = setup_coherent_ht_domain();
 171
 172         // automatically set that for you, but you might meet tight space
 173         needs_reset |= ht_setup_chains_x();
 174
 175         if (needs_reset) {
 176                 print_info("ht reset -\r\n");
 177                 soft_reset();
 178         }
 179
 180         enable_smbus();
 181         memreset_setup();
 182         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 183
 184
 185
 186 }