src/mainboard/tyan/s2885/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  24 #include "cpu/x86/bist.h"
  25 #include "cpu/amd/dualcore/dualcore.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 /* Look up a which bus a given node/link combination is on.
  30  * return 0 when we can't find the answer.
  31  */
  32 static unsigned node_link_to_bus(unsigned node, unsigned link)
  33 {
  34         unsigned reg;
  35
  36         for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
  37                 unsigned config_map;
  38                 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
  39                 if ((config_map & 3) != 3) {
  40                         continue;
  41                 }
  42                 if ((((config_map >> 4) & 7) == node) &&
  43                         (((config_map >> 8) & 3) == link))
  44                 {
  45                         return (config_map >> 16) & 0xff;
  46                 }
  47         }
  48         return 0;
  49 }
  50
  51 static void hard_reset(void)
  52 {
  53         device_t dev;
  54
  55         /* Find the device */
  56         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
  57
  58         set_bios_reset();
  59
  60         /* enable cf9 */
  61         pci_write_config8(dev, 0x41, 0xf1);
  62         /* reset */
  63         outb(0x0e, 0x0cf9);
  64 }
  65
  66 static void soft_reset(void)
  67 {
  68         device_t dev;
  69
  70         /* Find the device */
  71         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
  72
  73         set_bios_reset();
  74         pci_write_config8(dev, 0x47, 1);
  75 }
  76
  77 static void memreset_setup(void)
  78 {
  79    if (is_cpu_pre_c0()) {
  80         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  81    }
  82    else {
  83         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  84    }
  85         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  86 }
  87
  88 static void memreset(int controllers, const struct mem_controller *ctrl)
  89 {
  90    if (is_cpu_pre_c0()) {
  91         udelay(800);
  92         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  93         udelay(90);
  94    }
  95 }
  96
  97 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  98 {
  99         /* nothing to do */
 100 }
 101
 102 static inline int spd_read_byte(unsigned device, unsigned address)
 103 {
 104         return smbus_read_byte(device, address);
 105 }
 106
 107 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 108 #define QRANK_DIMM_SUPPORT 1
 109 #include "northbridge/amd/amdk8/raminit.c"
 110
 111 #if 0
 112         #define ENABLE_APIC_EXT_ID 1
 113         #define APIC_ID_OFFSET 0x10
 114         #define LIFT_BSP_APIC_ID 0
 115 #else
 116         #define ENABLE_APIC_EXT_ID 0
 117 #endif
 118 #include "northbridge/amd/amdk8/coherent_ht.c"
 119 #include "sdram/generic_sdram.c"
 120
 121 /* tyan does not want the default */
 122 #include "resourcemap.c"
 123
 124 #define FIRST_CPU  1
 125 #define SECOND_CPU 1
 126 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 127
 128 static void main(unsigned long bist)
 129 {
 130         static const struct mem_controller cpu[] = {
 131 #if FIRST_CPU
 132                 {
 133                         .node_id = 0,
 134                         .f0 = PCI_DEV(0, 0x18, 0),
 135                         .f1 = PCI_DEV(0, 0x18, 1),
 136                         .f2 = PCI_DEV(0, 0x18, 2),
 137                         .f3 = PCI_DEV(0, 0x18, 3),
 138                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 139                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 140                 },
 141 #endif
 142 #if SECOND_CPU
 143                 {
 144                         .node_id = 1,
 145                         .f0 = PCI_DEV(0, 0x19, 0),
 146                         .f1 = PCI_DEV(0, 0x19, 1),
 147                         .f2 = PCI_DEV(0, 0x19, 2),
 148                         .f3 = PCI_DEV(0, 0x19, 3),
 149                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 150                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 151                 },
 152 #endif
 153         };
 154
 155         int needs_reset;
 156
 157         if (bist == 0) {
 158                 k8_init_and_stop_secondaries();
 159         }
 160
 161         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 162         uart_init();
 163         console_init();
 164
 165         /* Halt if there was a built in self test failure */
 166         report_bist_failure(bist);
 167
 168         setup_s2885_resource_map();
 169         needs_reset = setup_coherent_ht_domain();
 170
 171         // automatically set that for you, but you might meet tight space
 172         needs_reset |= ht_setup_chains_x();
 173
 174         if (needs_reset) {
 175                 print_info("ht reset -\r\n");
 176                 soft_reset();
 177         }
 178
 179         enable_smbus();
 180         memreset_setup();
 181         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 182
 183
 184
 185 }