1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_XIP_ROM_SIZE
24 uses CONFIG_XIP_ROM_BASE
25 uses CONFIG_STACK_SIZE
27 uses CONFIG_USE_OPTION_TABLE
28 uses CONFIG_LB_CKS_RANGE_START
29 uses CONFIG_LB_CKS_RANGE_END
30 uses CONFIG_LB_CKS_LOC
31 uses CONFIG_MAINBOARD_PART_NUMBER
32 uses CONFIG_MAINBOARD_VENDOR
34 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
35 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
36 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
42 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
43 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
45 uses CONFIG_HAVE_INIT_TIMER
48 uses CONFIG_CROSS_COMPILE
52 uses CONFIG_CONSOLE_VGA
53 uses CONFIG_PCI_ROM_RUN
54 uses CONFIG_HW_MEM_HOLE_SIZEK
56 uses CONFIG_USE_DCACHE_RAM
57 uses CONFIG_DCACHE_RAM_BASE
58 uses CONFIG_DCACHE_RAM_SIZE
60 uses CONFIG_USE_PRINTK_IN_CAR
62 uses CONFIG_ENABLE_APIC_EXT_ID
63 uses CONFIG_APIC_ID_OFFSET
64 uses CONFIG_LIFT_BSP_APIC_ID
66 uses CONFIG_HT_CHAIN_UNITID_BASE
67 uses CONFIG_HT_CHAIN_END_UNITID_BASE
68 uses CONFIG_SB_HT_CHAIN_ON_BUS0
69 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
76 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
78 default CONFIG_ROM_SIZE=524288
81 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
83 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
86 ## Build code for the fallback boot
88 default CONFIG_HAVE_FALLBACK_BOOT=1
91 ## Build code to reset the motherboard from coreboot
93 default CONFIG_HAVE_HARD_RESET=1
96 ## Build code to export a programmable irq routing table
98 default CONFIG_GENERATE_PIRQ_TABLE=1
99 default CONFIG_IRQ_SLOT_COUNT=11
102 ## Build code to export an x86 MP table
103 ## Useful for specifying IRQ routing values
105 default CONFIG_GENERATE_MP_TABLE=1
108 ## Build code to export a CMOS option table
110 default CONFIG_HAVE_OPTION_TABLE=1
113 ## Move the default coreboot cmos range off of AMD RTC registers
115 default CONFIG_LB_CKS_RANGE_START=49
116 default CONFIG_LB_CKS_RANGE_END=122
117 default CONFIG_LB_CKS_LOC=123
120 ## Build code for SMP support
121 ## Only worry about 2 micro processors
124 default CONFIG_MAX_CPUS=4
125 default CONFIG_MAX_PHYSICAL_CPUS=2
126 default CONFIG_LOGICAL_CPUS=1
128 ##HT Unit ID offset, default is 1, the typical one
129 default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
131 ##real SB Unit ID, default is 0x20, mean dont touch it at last
132 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
134 #make the SB HT chain on bus 0, default is not (0)
135 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
137 ##only offset for SB chain?, default is yes(1)
138 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
141 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
144 default CONFIG_CONSOLE_VGA=1
145 default CONFIG_PCI_ROM_RUN=1
149 ## enable CACHE_AS_RAM specifics
151 default CONFIG_USE_DCACHE_RAM=1
152 default CONFIG_DCACHE_RAM_BASE=0xcf000
153 default CONFIG_DCACHE_RAM_SIZE=0x1000
154 default CONFIG_USE_INIT=0
156 default CONFIG_ENABLE_APIC_EXT_ID=1
157 default CONFIG_APIC_ID_OFFSET=0x10
158 default CONFIG_LIFT_BSP_APIC_ID=0
161 ## Build code to setup a generic IOAPIC
163 default CONFIG_IOAPIC=1
166 ## Clean up the motherboard id strings
168 default CONFIG_MAINBOARD_PART_NUMBER="s2885"
169 default CONFIG_MAINBOARD_VENDOR="Tyan"
170 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
171 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
174 ### coreboot layout values
177 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
178 default CONFIG_ROM_IMAGE_SIZE = 65536
181 ## Use a small 8K stack
183 default CONFIG_STACK_SIZE=0x2000
186 ## Use a small 16K heap
188 default CONFIG_HEAP_SIZE=0x4000
191 ## Only use the option table in a normal image
193 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
196 ## Coreboot C code runs at this location in RAM
198 default CONFIG_RAMBASE=0x00004000
201 ## Load the payload from the ROM
203 default CONFIG_ROM_PAYLOAD = 1
206 ### Defaults of options that you may want to override in the target config file
210 ## The default compiler
212 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
216 ## Disable the gdb stub by default
218 default CONFIG_GDB_STUB=0
220 default CONFIG_USE_PRINTK_IN_CAR=1
223 ## The Serial Console
226 # To Enable the Serial Console
227 default CONFIG_CONSOLE_SERIAL8250=1
229 ## Select the serial console baud rate
230 default CONFIG_TTYS0_BAUD=115200
231 #default CONFIG_TTYS0_BAUD=57600
232 #default CONFIG_TTYS0_BAUD=38400
233 #default CONFIG_TTYS0_BAUD=19200
234 #default CONFIG_TTYS0_BAUD=9600
235 #default CONFIG_TTYS0_BAUD=4800
236 #default CONFIG_TTYS0_BAUD=2400
237 #default CONFIG_TTYS0_BAUD=1200
239 # Select the serial console base port
240 default CONFIG_TTYS0_BASE=0x3f8
242 # Select the serial protocol
243 # This defaults to 8 data bits, 1 stop bit, and no parity
244 default CONFIG_TTYS0_LCS=0x3
247 ### Select the coreboot loglevel
249 ## EMERG 1 system is unusable
250 ## ALERT 2 action must be taken immediately
251 ## CRIT 3 critical conditions
252 ## ERR 4 error conditions
253 ## WARNING 5 warning conditions
254 ## NOTICE 6 normal but significant condition
255 ## INFO 7 informational
256 ## CONFIG_DEBUG 8 debug-level messages
257 ## SPEW 9 Way too many details
259 ## Request this level of debugging output
260 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
261 ## At a maximum only compile in this level of debugging
262 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
265 ## Select power on after power fail setting
266 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"