4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
34 uses MAINBOARD_PART_NUMBER
37 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
44 uses DEFAULT_CONSOLE_LOGLEVEL
45 uses MAXIMUM_CONSOLE_LOGLEVEL
46 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
63 uses CONFIG_USE_PRINTK_IN_CAR
65 uses ENABLE_APIC_EXT_ID
69 uses HT_CHAIN_UNITID_BASE
70 uses HT_CHAIN_END_UNITID_BASE
71 uses SB_HT_CHAIN_ON_BUS0
72 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
74 uses CONFIG_LB_MEM_TOPK
81 ## ROM_SIZE is the size of boot ROM that this board will use.
83 default ROM_SIZE=524288
86 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
88 #default FALLBACK_SIZE=131072
90 default FALLBACK_SIZE=0x40000
93 ## Build code for the fallback boot
95 default HAVE_FALLBACK_BOOT=1
98 ## Build code to reset the motherboard from coreboot
100 default HAVE_HARD_RESET=1
103 ## Build code to export a programmable irq routing table
105 default HAVE_PIRQ_TABLE=1
106 default IRQ_SLOT_COUNT=11
109 ## Build code to export an x86 MP table
110 ## Useful for specifying IRQ routing values
112 default HAVE_MP_TABLE=1
115 ## Build code to export a CMOS option table
117 default HAVE_OPTION_TABLE=1
120 ## Move the default coreboot cmos range off of AMD RTC registers
122 default LB_CKS_RANGE_START=49
123 default LB_CKS_RANGE_END=122
124 default LB_CKS_LOC=123
127 ## Build code for SMP support
128 ## Only worry about 2 micro processors
131 default CONFIG_MAX_CPUS=4
132 default CONFIG_MAX_PHYSICAL_CPUS=2
133 default CONFIG_LOGICAL_CPUS=1
135 ##HT Unit ID offset, default is 1, the typical one
136 default HT_CHAIN_UNITID_BASE=0x0a
138 ##real SB Unit ID, default is 0x20, mean dont touch it at last
139 default HT_CHAIN_END_UNITID_BASE=0x06
141 #make the SB HT chain on bus 0, default is not (0)
142 default SB_HT_CHAIN_ON_BUS0=2
144 ##only offset for SB chain?, default is yes(1)
145 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
148 default HW_MEM_HOLE_SIZEK=0x100000
151 default CONFIG_CONSOLE_VGA=1
152 default CONFIG_PCI_ROM_RUN=1
156 ## enable CACHE_AS_RAM specifics
158 default USE_DCACHE_RAM=1
159 default DCACHE_RAM_BASE=0xcf000
160 default DCACHE_RAM_SIZE=0x1000
161 default CONFIG_USE_INIT=0
163 default ENABLE_APIC_EXT_ID=1
164 default APIC_ID_OFFSET=0x10
165 default LIFT_BSP_APIC_ID=0
168 ## Build code to setup a generic IOAPIC
170 default CONFIG_IOAPIC=1
173 ## Clean up the motherboard id strings
175 default MAINBOARD_PART_NUMBER="s2885"
176 default MAINBOARD_VENDOR="Tyan"
177 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
178 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
181 ### coreboot layout values
184 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
185 default ROM_IMAGE_SIZE = 65536
188 ## Use a small 8K stack
190 default STACK_SIZE=0x2000
193 ## Use a small 16K heap
195 default HEAP_SIZE=0x4000
198 ## Only use the option table in a normal image
200 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
203 ## Coreboot C code runs at this location in RAM
205 default _RAMBASE=0x00004000
208 ## Load the payload from the ROM
210 default CONFIG_ROM_PAYLOAD = 1
213 ### Defaults of options that you may want to override in the target config file
217 ## The default compiler
219 default CC="$(CROSS_COMPILE)gcc -m32"
223 ## Disable the gdb stub by default
225 default CONFIG_GDB_STUB=0
227 default CONFIG_USE_PRINTK_IN_CAR=1
230 ## The Serial Console
233 # To Enable the Serial Console
234 default CONFIG_CONSOLE_SERIAL8250=1
236 ## Select the serial console baud rate
237 default TTYS0_BAUD=115200
238 #default TTYS0_BAUD=57600
239 #default TTYS0_BAUD=38400
240 #default TTYS0_BAUD=19200
241 #default TTYS0_BAUD=9600
242 #default TTYS0_BAUD=4800
243 #default TTYS0_BAUD=2400
244 #default TTYS0_BAUD=1200
246 # Select the serial console base port
247 default TTYS0_BASE=0x3f8
249 # Select the serial protocol
250 # This defaults to 8 data bits, 1 stop bit, and no parity
251 default TTYS0_LCS=0x3
254 ### Select the coreboot loglevel
256 ## EMERG 1 system is unusable
257 ## ALERT 2 action must be taken immediately
258 ## CRIT 3 critical conditions
259 ## ERR 4 error conditions
260 ## WARNING 5 warning conditions
261 ## NOTICE 6 normal but significant condition
262 ## INFO 7 informational
263 ## DEBUG 8 debug-level messages
264 ## SPEW 9 Way too many details
266 ## Request this level of debugging output
267 default DEFAULT_CONSOLE_LOGLEVEL=8
268 ## At a maximum only compile in this level of debugging
269 default MAXIMUM_CONSOLE_LOGLEVEL=8
272 ## Select power on after power fail setting
273 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
280 default CONFIG_CBFS=0