src/mainboard/tyan/s2885/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses MAINBOARD
   5 uses ARCH
   6 #
   7 #
   8 ###
   9 ### Set all of the defaults for an x86 architecture
  10 ###
  11 #
  12 #
  13 ###
  14 ### Build the objects we have code for in this directory.
  15 ###
  16 ##object mainboard.o
  17 config chip.h
  18 register "fixup_scsi" = "1"
  19 register "fixup_vga" = "1"
  20
  21 driver mainboard.o
  22 driver broadcom_nic.o
  23 driver ti_firewire.o
  24 driver adaptec_scsi.o
  25 driver si_sata.o
  26 driver intel_nic.o
  27 object reset.o
  28 if HAVE_MP_TABLE object mptable.o end
  29 if HAVE_PIRQ_TABLE object irq_tables.o end
  30 #
  31 arch i386 end
  32 #cpu k8 end
  33 #
  34 ###
  35 ### Build our 16 bit and 32 bit linuxBIOS entry code
  36 ###
  37 mainboardinit cpu/i386/entry16.inc
  38 mainboardinit cpu/i386/entry32.inc
  39 ldscript /cpu/i386/entry16.lds
  40 ldscript /cpu/i386/entry32.lds
  41 #
  42 ###
  43 ### Build our reset vector (This is where linuxBIOS is entered)
  44 ###
  45 if USE_FALLBACK_IMAGE
  46         mainboardinit cpu/i386/reset16.inc
  47         ldscript /cpu/i386/reset16.lds
  48 else
  49         mainboardinit cpu/i386/reset32.inc
  50         ldscript /cpu/i386/reset32.lds
  51 end
  52 #
  53 #### Should this be in the northbridge code?
  54 mainboardinit arch/i386/lib/cpu_reset.inc
  55 #
  56 ###
  57 ### Include an id string (For safe flashing)
  58 ###
  59 mainboardinit arch/i386/lib/id.inc
  60 ldscript /arch/i386/lib/id.lds
  61 #
  62 ####
  63 #### This is the early phase of linuxBIOS startup
  64 #### Things are delicate and we test to see if we should
  65 #### failover to another image.
  66 ####
  67 #option MAX_REBOOT_CNT=2
  68 if USE_FALLBACK_IMAGE
  69   ldscript /arch/i386/lib/failover.lds
  70 end
  71 #
  72 ###
  73 ### Setup our mtrrs
  74 ###
  75 mainboardinit cpu/k8/earlymtrr.inc
  76 ###
  77 ### Only the bootstrap cpu makes it here.
  78 ### Failover if we need to
  79 ###
  80 #
  81 if USE_FALLBACK_IMAGE
  82   mainboardinit ./failover.inc
  83 end
  84
  85 #
  86 #
  87 ###
  88 ### Setup the serial port
  89 ###
  90 #mainboardinit superiowinbond/w83627hf/setup_serial.inc
  91 mainboardinit pc80/serial.inc
  92 mainboardinit arch/i386/lib/console.inc
  93 #
  94 ####
  95 #### O.k. We aren't just an intermediary anymore!
  96 ####
  97 #
  98 ###
  99 ### When debugging disable the watchdog timer
 100 ###
 101 ##option MAXIMUM_CONSOLE_LOGLEVEL=7
 102 #default MAXIMUM_CONSOLE_LOGLEVEL=7
 103 #
 104 #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
 105 #
 106 ###
 107 ### Romcc output
 108 ###
 109 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
 110 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
 111 #mainboardinit .failover.inc
 112
 113 makerule ./failover.E
 114         depends "$(MAINBOARD)/failover.c"
 115         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 116 end
 117
 118 makerule ./failover.inc
 119         depends "./romcc ./failover.E"
 120         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 121
 122 makerule ./auto.E
 123         depends "$(MAINBOARD)/auto.c"
 124         action  "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 125 end
 126 makerule ./auto.inc
 127         depends "./romcc ./auto.E"
 128         action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 129 #       action  "./romcc -mcpu=k8  -O ./auto.E > auto.inc"
 130 end
 131 mainboardinit cpu/k8/enable_mmx_sse.inc
 132 mainboardinit ./auto.inc
 133 mainboardinit cpu/k8/disable_mmx_sse.inc
 134 #
 135 ###
 136 ### Include the secondary Configuration files
 137 ###
 138 northbridge amd/amdk8 "mc0"
 139         pci 0:18.0
 140         pci 0:18.0
 141         pci 0:18.0
 142         pci 0:18.1
 143         pci 0:18.2
 144         pci 0:18.3
 145         southbridge amd/amd8131 "amd8131" link 2
 146                 pci 0:0.0
 147                 pci 0:0.1
 148                 pci 0:1.0
 149                 pci 0:1.1
 150         end
 151         southbridge amd/amd8111 "amd8111" link 2
 152                 pci 0:0.0
 153                 pci 0:1.0 on
 154                 pci 0:1.1 on
 155                 pci 0:1.2 on
 156                 pci 0:1.3 on
 157                 pci 0:1.5 on
 158                 pci 0:1.6 off
 159                 pci 1:0.0 on
 160                 pci 1:0.1 on
 161                 pci 1:0.2 on
 162                 pci 1:1.0 off
 163
 164         end
 165         southbridge amd/amd8151 "amd8151" link 0
 166                 pci 0:0.0
 167                 pci 0:1.0
 168         end
 169 end
 170
 171 northbridge amd/amdk8 "mc1"
 172         pci 0:19.0
 173         pci 0:19.0
 174         pci 0:19.0
 175         pci 0:19.1
 176         pci 0:19.2
 177         pci 0:19.3
 178 end
 179
 180 #northbridge amd/amdk8
 181 #end
 182 #southbridge amd/amd8111 "amd8111"
 183 #end
 184 #southbridge amd/amd8131 "amd8131"
 185 #end
 186 #southbridge amd/amd8151 "amd8151"
 187 #end
 188
 189 #mainboardinit archi386/smp/secondary.inc
 190 #superio NSC/pc87360
 191 #       register "com1" = "{1}"
 192 #       register "lpt" = "{1}"
 193 #end
 194 dir /pc80
 195 ##dir /src/superio/winbond/w83627hf
 196 #dir /bioscall
 197 #dir /cpu/k8
 198 cpu k8 "cpu0"
 199   register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
 200   register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 201 end
 202
 203 cpu k8 "cpu1"
 204 end
 205