src/mainboard/tyan/s2885/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses MAINBOARD
   5 uses ARCH
   6 #
   7 #
   8 ###
   9 ### Set all of the defaults for an x86 architecture
  10 ###
  11 #
  12 #
  13 ###
  14 ### Build the objects we have code for in this directory.
  15 ###
  16 config chip.h
  17 register "fixup_scsi" = "1"
  18 register "fixup_vga" = "1"
  19
  20 driver mainboard.o
  21 driver broadcom_nic.o
  22 driver ti_firewire.o
  23 driver adaptec_scsi.o
  24 driver si_sata.o
  25 driver intel_nic.o
  26 object reset.o
  27 if HAVE_MP_TABLE object mptable.o end
  28 if HAVE_PIRQ_TABLE object irq_tables.o end
  29 #
  30 arch i386 end
  31 #cpu k8 end
  32 #
  33 ###
  34 ### Build our 16 bit and 32 bit linuxBIOS entry code
  35 ###
  36 mainboardinit cpu/i386/entry16.inc
  37 mainboardinit cpu/i386/entry32.inc
  38 ldscript /cpu/i386/entry16.lds
  39 ldscript /cpu/i386/entry32.lds
  40 #
  41 ###
  42 ### Build our reset vector (This is where linuxBIOS is entered)
  43 ###
  44 if USE_FALLBACK_IMAGE
  45         mainboardinit cpu/i386/reset16.inc
  46         ldscript /cpu/i386/reset16.lds
  47 else
  48         mainboardinit cpu/i386/reset32.inc
  49         ldscript /cpu/i386/reset32.lds
  50 end
  51 #
  52 #### Should this be in the northbridge code?
  53 mainboardinit arch/i386/lib/cpu_reset.inc
  54 #
  55 ###
  56 ### Include an id string (For safe flashing)
  57 ###
  58 mainboardinit arch/i386/lib/id.inc
  59 ldscript /arch/i386/lib/id.lds
  60 #
  61 ####
  62 #### This is the early phase of linuxBIOS startup
  63 #### Things are delicate and we test to see if we should
  64 #### failover to another image.
  65 ####
  66 #option MAX_REBOOT_CNT=2
  67 if USE_FALLBACK_IMAGE
  68   ldscript /arch/i386/lib/failover.lds
  69 end
  70 #
  71 ###
  72 ### Setup our mtrrs
  73 ###
  74 mainboardinit cpu/k8/earlymtrr.inc
  75 ###
  76 ### Only the bootstrap cpu makes it here.
  77 ### Failover if we need to
  78 ###
  79 #
  80 if USE_FALLBACK_IMAGE
  81   mainboardinit ./failover.inc
  82 end
  83
  84 #
  85 #
  86 ###
  87 ### Setup the serial port
  88 ###
  89 #mainboardinit superiowinbond/w83627hf/setup_serial.inc
  90 mainboardinit pc80/serial.inc
  91 mainboardinit arch/i386/lib/console.inc
  92 #
  93 ####
  94 #### O.k. We aren't just an intermediary anymore!
  95 ####
  96 #
  97 ###
  98 ### When debugging disable the watchdog timer
  99 ###
 100 ##option MAXIMUM_CONSOLE_LOGLEVEL=7
 101 #default MAXIMUM_CONSOLE_LOGLEVEL=7
 102 #
 103 #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
 104 #
 105 ###
 106 ### Romcc output
 107 ###
 108 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
 109 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
 110 #mainboardinit .failover.inc
 111
 112 makerule ./failover.E
 113         depends "$(MAINBOARD)/failover.c"
 114         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 115 end
 116
 117 makerule ./failover.inc
 118         depends "./romcc ./failover.E"
 119         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 120
 121 makerule ./auto.E
 122         depends "$(MAINBOARD)/auto.c"
 123         action  "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 124 end
 125 makerule ./auto.inc
 126         depends "./romcc ./auto.E"
 127         action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 128 #       action  "./romcc -mcpu=k8  -O ./auto.E > auto.inc"
 129 end
 130 mainboardinit cpu/k8/enable_mmx_sse.inc
 131 mainboardinit ./auto.inc
 132 mainboardinit cpu/k8/disable_mmx_sse.inc
 133 #
 134 ###
 135 ### Include the secondary Configuration files
 136 ###
 137 northbridge amd/amdk8 "mc0"
 138         pci 0:18.0
 139         pci 0:18.0
 140         pci 0:18.0
 141         pci 0:18.1
 142         pci 0:18.2
 143         pci 0:18.3
 144         southbridge amd/amd8131 "amd8131"
 145                 pci 0:0.0
 146                 pci 0:0.1
 147                 pci 0:1.0
 148                 pci 0:1.1
 149         end
 150         southbridge amd/amd8111 "amd8111"
 151                 pci 0:0.0
 152                 pci 0:1.0
 153                 pci 0:1.1
 154                 pci 0:1.2
 155                 pci 0:1.3
 156                 pci 0:1.5
 157                 pci 0:1.6
 158         end
 159         southbridge amd/amd8151 "amd8151"
 160                 pci 2:0.0
 161                 pci 2:1.0
 162         end
 163 end
 164
 165 northbridge amd/amdk8 "mc1"
 166         pci 0:19.0
 167         pci 0:19.0
 168         pci 0:19.0
 169         pci 0:19.1
 170         pci 0:19.2
 171         pci 0:19.3
 172 end
 173
 174 #northbridge amd/amdk8
 175 #end
 176 #southbridge amd/amd8111 "amd8111"
 177 #end
 178 #southbridge amd/amd8131 "amd8131"
 179 #end
 180 #southbridge amd/amd8151 "amd8151"
 181 #end
 182
 183 #mainboardinit archi386/smp/secondary.inc
 184 #superio NSC/pc87360
 185 #       register "com1" = "{1}"
 186 #       register "lpt" = "{1}"
 187 #end
 188 dir /pc80
 189 ##dir /src/superio/winbond/w83627hf
 190 dir /bioscall
 191 #dir /cpu/k8
 192 cpu k8 "cpu0"
 193   register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
 194   register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 195 end
 196
 197 cpu k8 "cpu1"
 198 end
 199