src/mainboard/tyan/s2885/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42
  43 dir /drivers/si/3114
  44
  45 if HAVE_MP_TABLE object mptable.o end
  46 if HAVE_PIRQ_TABLE object irq_tables.o end
  47 #object reset.o
  48
  49
  50 ##
  51 ## Romcc output
  52 ##
  53 makerule ./failover.E
  54         depends "$(MAINBOARD)/failover.c ./romcc"
  55         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  56 end
  57
  58 makerule ./failover.inc
  59         depends "$(MAINBOARD)/failover.c ./romcc"
  60         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  61 end
  62
  63 makerule ./auto.E
  64         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  65         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  66 end
  67 makerule ./auto.inc
  68         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  69         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  70 end
  71
  72 ##
  73 ## Build our 16 bit and 32 bit linuxBIOS entry code
  74 ##
  75 mainboardinit cpu/x86/16bit/entry16.inc
  76 mainboardinit cpu/x86/32bit/entry32.inc
  77 ldscript /cpu/x86/16bit/entry16.lds
  78 ldscript /cpu/x86/32bit/entry32.lds
  79
  80 ##
  81 ## Build our reset vector (This is where linuxBIOS is entered)
  82 ##
  83 if USE_FALLBACK_IMAGE
  84         mainboardinit cpu/x86/16bit/reset16.inc
  85         ldscript /cpu/x86/16bit/reset16.lds
  86 else
  87         mainboardinit cpu/x86/32bit/reset32.inc
  88         ldscript /cpu/x86/32bit/reset32.lds
  89 end
  90
  91 ### Should this be in the northbridge code?
  92 mainboardinit arch/i386/lib/cpu_reset.inc
  93
  94 ##
  95 ## Include an id string (For safe flashing)
  96 ##
  97 mainboardinit arch/i386/lib/id.inc
  98 ldscript /arch/i386/lib/id.lds
  99
 100 ###
 101 ### This is the early phase of linuxBIOS startup
 102 ### Things are delicate and we test to see if we should
 103 ### failover to another image.
 104 ###
 105 if USE_FALLBACK_IMAGE
 106         ldscript /arch/i386/lib/failover.lds
 107         mainboardinit ./failover.inc
 108 end
 109
 110 ###
 111 ### O.k. We aren't just an intermediary anymore!
 112 ###
 113
 114 ##
 115 ## Setup RAM
 116 ##
 117 mainboardinit cpu/x86/fpu/enable_fpu.inc
 118 mainboardinit cpu/x86/mmx/enable_mmx.inc
 119 mainboardinit cpu/x86/sse/enable_sse.inc
 120 mainboardinit ./auto.inc
 121 mainboardinit cpu/x86/sse/disable_sse.inc
 122 mainboardinit cpu/x86/mmx/disable_mmx.inc
 123
 124 ##
 125 ## Include the secondary Configuration files
 126 ##
 127 dir /pc80
 128
 129 if CONFIG_CHIP_NAME
 130         config chip.h
 131 end
 132
 133 # sample config for tyan/s2885
 134 chip northbridge/amd/amdk8/root_complex
 135         device pci_domain 0 on
 136                 chip northbridge/amd/amdk8
 137                         device pci 18.0 on # LDT0
 138                                 chip southbridge/amd/amd8151
 139                                         # the on/off keyword is mandatory
 140                                         device pci 0.0 on end
 141                                         device pci 1.0 on end
 142                                 end
 143                         end
 144                         device pci 18.0 on end # LDT1
 145                         device pci 18.0 on #  northbridge
 146                                 #  devices on link 2, link 2 == LDT 2
 147                                 chip southbridge/amd/amd8131
 148                                         # the on/off keyword is mandatory
 149                                         device pci 0.0 on end
 150                                         device pci 0.1 on end
 151                                         device pci 1.0 on end
 152                                         device pci 1.1 on end
 153                                 end
 154                                 chip southbridge/amd/amd8111
 155                                         # this "device pci 0.0" is the parent the next one
 156                                         # PCI bridge
 157                                         device pci 0.0 on
 158                                                 device pci 0.0 on end
 159                                                 device pci 0.1 on end
 160                                                 device pci 0.2 off end
 161                                                 device pci 1.0 off end
 162                                         end
 163                                         device pci 1.0 on
 164 #                                               chip drivers/generic/debug
 165 #                                                       device pnp 2.0 on end
 166 #                                                       device pnp 2.1 off end
 167 #                                                       device pnp 2.2 off end
 168 #                                                       device pnp 2.3 on end
 169 #                                               end
 170                                                 chip superio/winbond/w83627hf
 171                                                         device pnp 2e.0 on #  Floppy
 172                                                                 io 0x60 = 0x3f0
 173                                                                 irq 0x70 = 6
 174                                                                 drq 0x74 = 2
 175                                                         end
 176                                                         device pnp 2e.1 off #  Parallel Port
 177                                                                 io 0x60 = 0x378
 178                                                                 irq 0x70 = 7
 179                                                         end
 180                                                         device pnp 2e.2 on #  Com1
 181                                                                 io 0x60 = 0x3f8
 182                                                                 irq 0x70 = 4
 183                                                         end
 184                                                         device pnp 2e.3 off #  Com2
 185                                                                 io 0x60 = 0x2f8
 186                                                                 irq 0x70 = 3
 187                                                         end
 188                                                         device pnp 2e.5 on #  Keyboard
 189                                                                 io 0x60 = 0x60
 190                                                                 io 0x62 = 0x64
 191                                                                 irq 0x70 = 1
 192                                                                 irq 0x72 = 12
 193                                                         end
 194                                                         device pnp 2e.6 off #  CIR
 195                                                                 io 0x60 = 0x100
 196                                                         end
 197                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 198                                                                 io 0x60 = 0x201
 199                                                                 io 0x62 = 0x330
 200                                                                 irq 0x70 = 9
 201                                                         end
 202                                                         device pnp 2e.8 off end #  GPIO2
 203                                                         device pnp 2e.9 off end #  GPIO3
 204                                                         device pnp 2e.a off end #  ACPI
 205                                                         device pnp 2e.b on #  HW Monitor
 206                                                                 io 0x60 = 0x290
 207                                                                 irq 0x70 = 5
 208                                                         end
 209                                                 end
 210                                         end
 211                                         device pci 1.1 on end
 212                                         device pci 1.2 on end
 213                                         device pci 1.3 on end
 214                                         device pci 1.5 on end
 215                                         device pci 1.6 off end
 216                                         register "ide0_enable" = "1"
 217                                         register "ide1_enable" = "1"
 218                                 end
 219                         end #  device pci 18.0
 220
 221                         device pci 18.1 on end
 222                         device pci 18.2 on end
 223                         device pci 18.3 on
 224 #                                chip drivers/generic/debug
 225 #                                        device pnp 1.0 on end
 226 #                                        device pnp 1.1 off end
 227 #                                        device pnp 1.2 off end
 228 #                                        device pnp 1.3 on end
 229 #                                end
 230                         end
 231                 end
 232
 233                 chip northbridge/amd/amdk8
 234                         device pci 19.0 on end
 235                         device pci 19.0 on end
 236                         device pci 19.0 on end
 237                         device pci 19.1 on end
 238                         device pci 19.2 on end
 239                         device pci 19.3 on end
 240                 end
 241         end
 242         device apic_cluster 0 on
 243                 chip cpu/amd/socket_940
 244                         device apic 0 on end
 245                 end
 246                 chip cpu/amd/socket_940
 247                         device apic 1 on end
 248                 end
 249         end
 250
 251         chip drivers/generic/debug
 252                 device pnp 0.0 on end
 253                 device pnp 0.1 off end
 254                 device pnp 0.2 off end
 255                 device pnp 0.3 on end
 256         end
 257 end
 258