src/mainboard/tyan/s2885/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12
  13 #
  14 #
  15 ###
  16 ### Set all of the defaults for an x86 architecture
  17 ###
  18
  19 #
  20 #
  21 ###
  22 ### Build the objects we have code for in this directory.
  23 ###
  24
  25 config chip.h
  26 register "fixup_scsi" = "1"
  27 register "fixup_vga" = "1"
  28
  29
  30 ##
  31 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  32 ##
  33 default LB_CKS_RANGE_START=49
  34 default LB_CKS_RANGE_END=122
  35 default LB_CKS_LOC=123
  36
  37 driver mainboard.o
  38 #dir /drvers/adaptec/7902
  39 #dir /drivers/si/3114
  40 #dir /drivers/intel/82551
  41 driver ti_firewire.o
  42 #object reset.o
  43 if HAVE_MP_TABLE object mptable.o end
  44 if HAVE_PIRQ_TABLE object irq_tables.o end
  45 #
  46 default HARD_RESET_BUS=3
  47 default HARD_RESET_DEVICE=4
  48 default HARD_RESET_FUNCTION=0
  49 #
  50 #
  51 arch i386 end
  52
  53 #
  54 ###
  55 ### Build our 16 bit and 32 bit linuxBIOS entry code
  56 ###
  57 mainboardinit cpu/i386/entry16.inc
  58 mainboardinit cpu/i386/entry32.inc
  59 mainboardinit cpu/i386/bist32.inc
  60 ldscript /cpu/i386/entry16.lds
  61 ldscript /cpu/i386/entry32.lds
  62
  63 #
  64 ###
  65 ### Build our reset vector (This is where linuxBIOS is entered)
  66 ###
  67 if USE_FALLBACK_IMAGE
  68         mainboardinit cpu/i386/reset16.inc
  69         ldscript /cpu/i386/reset16.lds
  70 else
  71         mainboardinit cpu/i386/reset32.inc
  72         ldscript /cpu/i386/reset32.lds
  73 end
  74 #
  75 #### Should this be in the northbridge code?
  76 mainboardinit arch/i386/lib/cpu_reset.inc
  77 #
  78 ###
  79 ### Include an id string (For safe flashing)
  80 ###
  81 mainboardinit arch/i386/lib/id.inc
  82 ldscript /arch/i386/lib/id.lds
  83 #
  84 ####
  85 #### This is the early phase of linuxBIOS startup
  86 #### Things are delicate and we test to see if we should
  87 #### failover to another image.
  88 ####
  89 #option MAX_REBOOT_CNT=2
  90 if USE_FALLBACK_IMAGE
  91   ldscript /arch/i386/lib/failover.lds
  92 end
  93 #
  94 ###
  95 ### Setup our mtrrs
  96 ###
  97 mainboardinit cpu/k8/earlymtrr.inc
  98 ###
  99 ### Only the bootstrap cpu makes it here.
 100 ### Failover if we need to
 101 ###
 102 #
 103 if USE_FALLBACK_IMAGE
 104   mainboardinit ./failover.inc
 105 end
 106
 107 #
 108 #
 109 ###
 110 ### Setup the serial port
 111 ###
 112 mainboardinit pc80/serial.inc
 113 mainboardinit arch/i386/lib/console.inc
 114 mainboardinit cpu/i386/bist32_fail.inc
 115 #
 116 ####
 117 #### O.k. We aren't just an intermediary anymore!
 118 ####
 119 ###
 120 ### Romcc output
 121 ###
 122 makerule ./failover.E
 123         depends "$(MAINBOARD)/failover.c"
 124         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 125 end
 126
 127 makerule ./failover.inc
 128         depends "./romcc ./failover.E"
 129         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
 130 end
 131
 132 makerule ./auto.E
 133         depends "$(MAINBOARD)/auto.c option_table.h"
 134         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 135 end
 136
 137 makerule ./auto.inc
 138         depends "./romcc ./auto.E"
 139         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 140 end
 141
 142 mainboardinit cpu/k8/enable_mmx_sse.inc
 143 mainboardinit ./auto.inc
 144 mainboardinit cpu/k8/disable_mmx_sse.inc
 145
 146 #
 147 ###
 148 ### Include the secondary Configuration files
 149 ###
 150 dir /pc80
 151
 152 northbridge amd/amdk8 "mc0"
 153         pci 0:18.0
 154         pci 0:18.0
 155         pci 0:18.0
 156         pci 0:18.1
 157         pci 0:18.2
 158         pci 0:18.3
 159         southbridge amd/amd8131 "amd8131" link 2
 160                 pci 0:0.0
 161                 pci 0:0.1
 162                 pci 0:1.0
 163                 pci 0:1.1
 164         end
 165         southbridge amd/amd8111 "amd8111" link 2
 166                 pci 0:0.0
 167                 pci 0:1.0 on
 168                 pci 0:1.1 on
 169                 pci 0:1.2 on
 170                 pci 0:1.3 on
 171                 pci 0:1.5 on
 172                 pci 0:1.6 off
 173                 pci 1:0.0 on
 174                 pci 1:0.1 on
 175                 pci 1:0.2 on
 176                 pci 1:1.0 off
 177                 superio winbond/w83627hf link 1
 178                         pnp 2e.0 on #  Floppy
 179                                  io 0x60 = 0x3f0
 180                                 irq 0x70 = 6
 181                                 drq 0x74 = 2
 182                         pnp 2e.1 off #  Parallel Port
 183                                  io 0x60 = 0x378
 184                                 irq 0x70 = 7
 185                         pnp 2e.2 on #  Com1
 186                                  io 0x60 = 0x3f8
 187                                 irq 0x70 = 4
 188                         pnp 2e.3 off #  Com2
 189                                  io 0x60 = 0x2f8
 190                                 irq 0x70 = 3
 191                         pnp 2e.5 on #  Keyboard
 192                                  io 0x60 = 0x60
 193                                  io 0x62 = 0x64
 194                                irq 0x70 = 1
 195                                 irq 0x72 = 12
 196                         pnp 2e.6 off #  CIR
 197                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 198                         pnp 2e.8 off #  GPIO2
 199                         pnp 2e.9 off #  GPIO3
 200                         pnp 2e.a off #  ACPI
 201                         pnp 2e.b on #  HW Monitor
 202                                  io 0x60 = 0x290
 203                 end
 204         end
 205         southbridge amd/amd8151 "amd8151" link 0
 206                 pci 0:0.0
 207                 pci 0:1.0
 208         end
 209 end
 210
 211 northbridge amd/amdk8 "mc1"
 212         pci 0:19.0
 213         pci 0:19.0
 214         pci 0:19.0
 215         pci 0:19.1
 216         pci 0:19.2
 217         pci 0:19.3
 218 end
 219
 220 #dir /bioscall
 221
 222 cpu k8 "cpu0"
 223   register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
 224   register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 225 end
 226
 227 cpu k8 "cpu1"
 228 end
 229