1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
8 ## Build the objects we have code for in this directory.
15 if CONFIG_GENERATE_MP_TABLE object mptable.o end
16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
21 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
22 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
28 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
29 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
30 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
31 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
36 ## Build our 16 bit and 32 bit coreboot entry code
38 if CONFIG_USE_FALLBACK_IMAGE
39 mainboardinit cpu/x86/16bit/entry16.inc
40 ldscript /cpu/x86/16bit/entry16.lds
43 mainboardinit cpu/x86/32bit/entry32.inc
46 ldscript /cpu/x86/32bit/entry32.lds
50 ldscript /cpu/amd/car/cache_as_ram.lds
54 ## Build our reset vector (This is where coreboot is entered)
56 if CONFIG_USE_FALLBACK_IMAGE
57 mainboardinit cpu/x86/16bit/reset16.inc
58 ldscript /cpu/x86/16bit/reset16.lds
60 mainboardinit cpu/x86/32bit/reset32.inc
61 ldscript /cpu/x86/32bit/reset32.lds
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
73 mainboardinit cpu/amd/car/cache_as_ram.inc
76 ### This is the early phase of coreboot startup
77 ### Things are delicate and we test to see if we should
78 ### failover to another image.
80 if CONFIG_USE_FALLBACK_IMAGE
81 ldscript /arch/i386/lib/failover.lds
85 ### O.k. We aren't just an intermediary anymore!
94 mainboardinit ./auto.inc
98 ## Include the secondary Configuration files
102 # sample config for tyan/s2885
103 chip northbridge/amd/amdk8/root_complex
104 device apic_cluster 0 on
105 chip cpu/amd/socket_940
109 device pci_domain 0 on
110 chip northbridge/amd/amdk8
111 device pci 18.0 on # LDT0
112 chip southbridge/amd/amd8151
113 # the on/off keyword is mandatory
114 device pci 0.0 on end
115 device pci 1.0 on end
118 device pci 18.0 on end # LDT1
119 device pci 18.0 on # northbridge
120 # devices on link 2, link 2 == LDT 2
121 chip southbridge/amd/amd8131
122 # the on/off keyword is mandatory
124 chip drivers/pci/onboard
125 device pci 9.0 on end # broadcom 5703
128 device pci 0.1 on end
129 device pci 1.0 on end
130 device pci 1.1 on end
132 chip southbridge/amd/amd8111
133 # this "device pci 0.0" is the parent the next one
136 device pci 0.0 on end
137 device pci 0.1 on end
138 device pci 0.2 off end
139 device pci 1.0 off end
140 chip drivers/pci/onboard
141 device pci b.0 on end # SiI 3114
145 chip superio/winbond/w83627hf
146 device pnp 2e.0 on # Floppy
151 device pnp 2e.1 off # Parallel Port
155 device pnp 2e.2 on # Com1
159 device pnp 2e.3 on # Com2
163 device pnp 2e.5 on # Keyboard
169 device pnp 2e.6 off # CIR
172 device pnp 2e.7 off # GAME_MIDI_GIPO1
177 device pnp 2e.8 off end # GPIO2
178 device pnp 2e.9 off end # GPIO3
179 device pnp 2e.a off end # ACPI
180 device pnp 2e.b on # HW Monitor
186 device pci 1.1 on end
187 device pci 1.2 on end
189 chip drivers/generic/generic #dimm 0-0-0
192 chip drivers/generic/generic #dimm 0-0-1
195 chip drivers/generic/generic #dimm 0-1-0
198 chip drivers/generic/generic #dimm 0-1-1
201 chip drivers/generic/generic #dimm 1-0-0
204 chip drivers/generic/generic #dimm 1-0-1
207 chip drivers/generic/generic #dimm 1-1-0
210 chip drivers/generic/generic #dimm 1-1-1
214 device pci 1.5 on end
215 device pci 1.6 off end
216 register "ide0_enable" = "1"
217 register "ide1_enable" = "1"
219 end # device pci 18.0
221 device pci 18.1 on end
222 device pci 18.2 on end
223 device pci 18.3 on end
228 # chip drivers/generic/debug
229 # device pnp 0.0 off end
230 # device pnp 0.1 off end
231 # device pnp 0.2 off end
232 # device pnp 0.3 off end
233 # device pnp 0.4 off end
234 # device pnp 0.5 on end