src/mainboard/tyan/s2882/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "lib/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  27
  28 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  36
  37 static void memreset_setup(void)
  38 {
  39    if (is_cpu_pre_c0()) {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  41    }
  42    else {
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  44    }
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46 }
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl)
  49 {
  50    if (is_cpu_pre_c0()) {
  51         udelay(800);
  52         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  53         udelay(90);
  54    }
  55 }
  56
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59         /* nothing to do */
  60 }
  61
  62 static inline int spd_read_byte(unsigned device, unsigned address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67 #define QRANK_DIMM_SUPPORT 1
  68
  69 #include "northbridge/amd/amdk8/raminit.c"
  70 #include "northbridge/amd/amdk8/resourcemap.c"
  71 #include "northbridge/amd/amdk8/coherent_ht.c"
  72 #include "lib/generic_sdram.c"
  73
  74 #if CONFIG_LOGICAL_CPUS==1
  75 #define SET_NB_CFG_54 1
  76 #endif
  77 #include "cpu/amd/dualcore/dualcore.c"
  78
  79 #define FIRST_CPU  1
  80 #define SECOND_CPU 1
  81 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  82
  83 #include "cpu/amd/car/copy_and_run.c"
  84
  85 #include "cpu/amd/car/post_cache_as_ram.c"
  86
  87 #include "cpu/amd/model_fxx/init_cpus.c"
  88
  89 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  90 #include "northbridge/amd/amdk8/early_ht.c"
  91
  92 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  93 {
  94         static const struct mem_controller cpu[] = {
  95                 {
  96                         .node_id = 0,
  97                         .f0 = PCI_DEV(0, 0x18, 0),
  98                         .f1 = PCI_DEV(0, 0x18, 1),
  99                         .f2 = PCI_DEV(0, 0x18, 2),
 100                         .f3 = PCI_DEV(0, 0x18, 3),
 101                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 102                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 103                 },
 104 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 105                 {
 106                         .node_id = 1,
 107                         .f0 = PCI_DEV(0, 0x19, 0),
 108                         .f1 = PCI_DEV(0, 0x19, 1),
 109                         .f2 = PCI_DEV(0, 0x19, 2),
 110                         .f3 = PCI_DEV(0, 0x19, 3),
 111                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 112                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 113                 },
 114 #endif
 115         };
 116
 117         int needs_reset;
 118
 119         if (!cpu_init_detectedx && boot_cpu()) {
 120                 /* Nothing special needs to be done to find bus 0 */
 121                 /* Allow the HT devices to be found */
 122
 123                 enumerate_ht_chain();
 124
 125                 amd8111_enable_rom();
 126         }
 127
 128         if (bist == 0) {
 129                 init_cpus(cpu_init_detectedx);
 130         }
 131
 132
 133         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 134         uart_init();
 135         console_init();
 136
 137         /* Halt if there was a built in self test failure */
 138         report_bist_failure(bist);
 139
 140         setup_default_resource_map();
 141
 142         needs_reset = setup_coherent_ht_domain();
 143
 144 #if CONFIG_LOGICAL_CPUS==1
 145         // It is said that we should start core1 after all core0 launched
 146         start_other_cores();
 147 #endif
 148         // automatically set that for you, but you might meet tight space
 149         needs_reset |= ht_setup_chains_x();
 150
 151         if (needs_reset) {
 152                 print_info("ht reset -\r\n");
 153                 soft_reset();
 154         }
 155
 156         enable_smbus();
 157
 158         memreset_setup();
 159         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 160
 161         post_cache_as_ram();
 162
 163 }
 164