1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
12 static unsigned node_link_to_bus(unsigned node, unsigned link)
17 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
21 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
26 config_map = pci_read_config32(dev, reg);
27 if ((config_map & 3) != 3) {
30 dst_node = (config_map >> 4) & 7;
31 dst_link = (config_map >> 8) & 3;
32 bus_base = (config_map >> 16) & 0xff;
34 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
35 dst_node, dst_link, bus_base,
38 if ((dst_node == node) && (dst_link == link))
46 static void *smp_write_config_table(void *v)
48 static const char sig[4] = "PCMP";
49 static const char oem[8] = "COREBOOT";
50 static const char productid[12] = "S2882 ";
51 struct mp_config_table *mc;
53 unsigned char bus_num;
54 unsigned char bus_isa;
55 unsigned char bus_chain_0;
56 unsigned char bus_8131_1;
57 unsigned char bus_8131_2;
58 unsigned char bus_8111_1;
61 unsigned apicid_8131_1;
62 unsigned apicid_8131_2;
64 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
65 memset(mc, 0, sizeof(*mc));
67 memcpy(mc->mpc_signature, sig, sizeof(sig));
68 mc->mpc_length = sizeof(*mc); /* initially just the header */
70 mc->mpc_checksum = 0; /* not yet computed */
71 memcpy(mc->mpc_oem, oem, sizeof(oem));
72 memcpy(mc->mpc_productid, productid, sizeof(productid));
75 mc->mpc_entry_count = 0; /* No entries yet... */
76 mc->mpc_lapic = LAPIC_ADDR;
81 smp_write_processors(mc);
86 bus_chain_0 = node_link_to_bus(0, 0);
87 if (bus_chain_0 == 0) {
88 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
93 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
95 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
96 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
100 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
106 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
108 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
112 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
117 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
119 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
123 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
129 /* define bus and isa numbers */
130 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
131 smp_write_bus(mc, bus_num, "PCI ");
133 smp_write_bus(mc, bus_isa, "ISA ");
136 /*I/O APICs: APIC ID Version State Address*/
137 #if CONFIG_LOGICAL_CPUS==1
138 apicid_base = get_apicid_base(3);
140 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
142 apicid_8111 = apicid_base+0;
143 apicid_8131_1 = apicid_base+1;
144 apicid_8131_2 = apicid_base+2;
146 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
149 struct resource *res;
150 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
152 res = find_resource(dev, PCI_BASE_ADDRESS_0);
154 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
157 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
159 res = find_resource(dev, PCI_BASE_ADDRESS_0);
161 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
167 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
168 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc);
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd);
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13);
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
188 //On Board ATI Display Adapter
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
199 //Onboard SI Serial ATA
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
202 //Onboard Intel 82551 10/100M NIC
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
207 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
213 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
214 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
215 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
216 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
220 //Onboard adaptec scsi
221 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
222 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
225 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
226 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
230 //Slot 1 PCI-X 133/100/66
231 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
232 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
233 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
234 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
236 //Slot 2 PCI-X 133/100/66
237 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
238 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
239 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
240 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
243 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
244 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
245 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
246 /* There is no extension information... */
248 /* Compute the checksums */
249 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
250 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
251 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
252 mc, smp_next_mpe_entry(mc));
253 return smp_next_mpe_entry(mc);
256 unsigned long write_smp_table(unsigned long addr)
259 v = smp_write_floating_table(addr);
260 return (unsigned long)smp_write_config_table(v);