1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
8 #if CONFIG_LOGICAL_CPUS==1
9 #include <cpu/amd/multicore.h>
12 static unsigned node_link_to_bus(unsigned node, unsigned link)
17 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
21 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
26 config_map = pci_read_config32(dev, reg);
27 if ((config_map & 3) != 3) {
30 dst_node = (config_map >> 4) & 7;
31 dst_link = (config_map >> 8) & 3;
32 bus_base = (config_map >> 16) & 0xff;
34 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
35 dst_node, dst_link, bus_base,
38 if ((dst_node == node) && (dst_link == link))
46 static void *smp_write_config_table(void *v)
48 struct mp_config_table *mc;
49 unsigned char bus_num;
50 unsigned char bus_isa;
51 unsigned char bus_chain_0;
52 unsigned char bus_8131_1;
53 unsigned char bus_8131_2;
54 unsigned char bus_8111_1;
57 unsigned apicid_8131_1;
58 unsigned apicid_8131_2;
60 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
62 mptable_init(mc, "S2882 ", LAPIC_ADDR);
64 smp_write_processors(mc);
69 bus_chain_0 = node_link_to_bus(0, 0);
70 if (bus_chain_0 == 0) {
71 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
76 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
78 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
79 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
83 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
89 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
91 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
95 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
100 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
102 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
106 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
112 /* define bus and isa numbers */
113 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
114 smp_write_bus(mc, bus_num, "PCI ");
116 smp_write_bus(mc, bus_isa, "ISA ");
119 /*I/O APICs: APIC ID Version State Address*/
120 #if CONFIG_LOGICAL_CPUS==1
121 apicid_base = get_apicid_base(3);
123 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
125 apicid_8111 = apicid_base+0;
126 apicid_8131_1 = apicid_base+1;
127 apicid_8131_2 = apicid_base+2;
129 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
132 struct resource *res;
133 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
135 res = find_resource(dev, PCI_BASE_ADDRESS_0);
137 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
140 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
142 res = find_resource(dev, PCI_BASE_ADDRESS_0);
144 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
150 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
152 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
160 //On Board ATI Display Adapter
161 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
171 //Onboard SI Serial ATA
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
174 //Onboard Intel 82551 10/100M NIC
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
186 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
192 //Onboard adaptec scsi
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
198 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
202 //Slot 1 PCI-X 133/100/66
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
204 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
205 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
208 //Slot 2 PCI-X 133/100/66
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
212 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
215 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
216 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
217 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
218 /* There is no extension information... */
220 /* Compute the checksums */
221 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
222 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
223 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
224 mc, smp_next_mpe_entry(mc));
225 return smp_next_mpe_entry(mc);
228 unsigned long write_smp_table(unsigned long addr)
231 v = smp_write_floating_table(addr);
232 return (unsigned long)smp_write_config_table(v);