src/mainboard/tyan/s2882/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #if CONFIG_USE_INIT == 0
  24 #include "lib/memcpy.c"
  25 #endif
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39 static void hard_reset(void)
  40 {
  41         device_t dev;
  42
  43         /* Find the device */
  44         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
  45
  46         set_bios_reset();
  47
  48         /* enable cf9 */
  49         pci_write_config8(dev, 0x41, 0xf1);
  50         /* reset */
  51         outb(0x0e, 0x0cf9);
  52 }
  53
  54 static void soft_reset(void)
  55 {
  56         device_t dev;
  57
  58         /* Find the device */
  59         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
  60
  61         set_bios_reset();
  62         pci_write_config8(dev, 0x47, 1);
  63 }
  64
  65 static void memreset_setup(void)
  66 {
  67    if (is_cpu_pre_c0()) {
  68         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  69    }
  70    else {
  71         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  72    }
  73         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  74 }
  75
  76 static void memreset(int controllers, const struct mem_controller *ctrl)
  77 {
  78    if (is_cpu_pre_c0()) {
  79         udelay(800);
  80         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  81         udelay(90);
  82    }
  83 }
  84
  85 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  86 {
  87         /* nothing to do */
  88 }
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92         return smbus_read_byte(device, address);
  93 }
  94
  95 #define K8_4RANK_DIMM_SUPPORT 1
  96
  97 #include "northbridge/amd/amdk8/raminit.c"
  98 #include "northbridge/amd/amdk8/resourcemap.c"
  99 #include "northbridge/amd/amdk8/coherent_ht.c"
 100 #include "sdram/generic_sdram.c"
 101
 102 #if CONFIG_LOGICAL_CPUS==1
 103 #define SET_NB_CFG_54 1
 104 #endif
 105 #include "cpu/amd/dualcore/dualcore.c"
 106
 107 #define FIRST_CPU  1
 108 #define SECOND_CPU 1
 109 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 110
 111 #include "cpu/amd/car/copy_and_run.c"
 112
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116
 117
 118 #if USE_FALLBACK_IMAGE == 1
 119
 120 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 121 #include "northbridge/amd/amdk8/early_ht.c"
 122
 123 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 124 {
 125         unsigned last_boot_normal_x = last_boot_normal();
 126
 127         /* Is this a cpu only reset? or Is this a secondary cpu? */
 128         if ((cpu_init_detectedx) || (!boot_cpu())) {
 129                 if (last_boot_normal_x) {
 130                         goto normal_image;
 131                 } else {
 132                         goto fallback_image;
 133                 }
 134         }
 135
 136         /* Nothing special needs to be done to find bus 0 */
 137         /* Allow the HT devices to be found */
 138
 139         enumerate_ht_chain();
 140
 141         amd8111_enable_rom();
 142
 143         /* Is this a deliberate reset by the bios */
 144         if (bios_reset_detected() && last_boot_normal_x) {
 145                 goto normal_image;
 146         }
 147         /* This is the primary cpu how should I boot? */
 148         else if (do_normal_boot()) {
 149                 goto normal_image;
 150         }
 151         else {
 152                 goto fallback_image;
 153         }
 154  normal_image:
 155         __asm__ volatile ("jmp __normal_image"
 156                 : /* outputs */
 157                 : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */
 158                 );
 159
 160  fallback_image:
 161         ;
 162 }
 163 #endif
 164
 165 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 166
 167 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 168 {
 169
 170 #if USE_FALLBACK_IMAGE == 1
 171         failover_process(bist, cpu_init_detectedx);
 172 #endif
 173         real_main(bist, cpu_init_detectedx);
 174
 175 }
 176
 177 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 178 {
 179         static const struct mem_controller cpu[] = {
 180                 {
 181                         .node_id = 0,
 182                         .f0 = PCI_DEV(0, 0x18, 0),
 183                         .f1 = PCI_DEV(0, 0x18, 1),
 184                         .f2 = PCI_DEV(0, 0x18, 2),
 185                         .f3 = PCI_DEV(0, 0x18, 3),
 186                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 187                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 188                 },
 189 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 190                 {
 191                         .node_id = 1,
 192                         .f0 = PCI_DEV(0, 0x19, 0),
 193                         .f1 = PCI_DEV(0, 0x19, 1),
 194                         .f2 = PCI_DEV(0, 0x19, 2),
 195                         .f3 = PCI_DEV(0, 0x19, 3),
 196                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 197                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 198                 },
 199 #endif
 200         };
 201
 202         int needs_reset;
 203         unsigned cpu_reset = 0;
 204
 205         if (bist == 0) {
 206                 init_cpus(cpu_init_detectedx);
 207         }
 208
 209
 210         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 211         uart_init();
 212         console_init();
 213
 214         /* Halt if there was a built in self test failure */
 215         report_bist_failure(bist);
 216
 217         setup_default_resource_map();
 218
 219         needs_reset = setup_coherent_ht_domain();
 220
 221 #if CONFIG_LOGICAL_CPUS==1
 222         // It is said that we should start core1 after all core0 launched
 223         start_other_cores();
 224 #endif
 225         // automatically set that for you, but you might meet tight space
 226         needs_reset |= ht_setup_chains_x();
 227
 228         if (needs_reset) {
 229                 print_info("ht reset -\r\n");
 230                 soft_reset();
 231         }
 232
 233         enable_smbus();
 234
 235         memreset_setup();
 236         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 237
 238         post_cache_as_ram(cpu_reset);
 239
 240 }