src/mainboard/tyan/s2882/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void soft2_reset(void)
  47 {
  48         set_bios_reset();
  49         pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
  50 }
  51
  52
  53 #define REV_B_RESET 0
  54 static void memreset_setup(void)
  55 {
  56    if (is_cpu_pre_c0()) {
  57         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  58    }
  59    else {
  60         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  61    }
  62         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  63 }
  64
  65 static void memreset(int controllers, const struct mem_controller *ctrl)
  66 {
  67    if (is_cpu_pre_c0()) {
  68         udelay(800);
  69         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  70         udelay(90);
  71    }
  72 }
  73
  74
  75 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  76 {
  77         /* Routing Table Node i
  78          *
  79          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  80          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  81          *
  82          * [ 0: 3] Request Route
  83          *     [0] Route to this node
  84          *     [1] Route to Link 0
  85          *     [2] Route to Link 1
  86          *     [3] Route to Link 2
  87          * [11: 8] Response Route
  88          *     [0] Route to this node
  89          *     [1] Route to Link 0
  90          *     [2] Route to Link 1
  91          *     [3] Route to Link 2
  92          * [19:16] Broadcast route
  93          *     [0] Route to this node
  94          *     [1] Route to Link 0
  95          *     [2] Route to Link 1
  96          *     [3] Route to Link 2
  97          */
  98
  99         uint32_t ret=0x00010101; /* default row entry */
 100         /* Link1 of CPU0 to Link1 of CPU1 */
 101         static const unsigned int rows_2p[2][2] = {
 102                 { 0x00050101, 0x00010404 },
 103                 { 0x00010404, 0x00050101 }
 104         };
 105 #if 0
 106         if(maxnodes>2) {
 107                 printo_debug("this mainboard is only designed for 2 cpus\r\n");
 108                 maxnodes=2;
 109         }
 110 #endif
 111
 112         if (!(node>=maxnodes || row>=maxnodes)) {
 113                 ret=rows_2p[node][row];
 114         }
 115
 116         return ret;
 117 }
 118
 119 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 120 {
 121         /* nothing to do */
 122 }
 123
 124 static inline int spd_read_byte(unsigned device, unsigned address)
 125 {
 126         return smbus_read_byte(device, address);
 127 }
 128
 129 #include "northbridge/amd/amdk8/raminit.c"
 130 #include "northbridge/amd/amdk8/coherent_ht.c"
 131 #include "sdram/generic_sdram.c"
 132 #include "northbridge/amd/amdk8/resourcemap.c"
 133
 134
 135 #define FIRST_CPU  1
 136 #define SECOND_CPU 1
 137 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 138 static void main(unsigned long bist)
 139 {
 140         /*
 141          * GPIO28 of 8111 will control H0_MEMRESET_L
 142          * GPIO29 of 8111 will control H1_MEMRESET_L
 143          */
 144         static const struct mem_controller cpu[] = {
 145 #if FIRST_CPU
 146                 {
 147                         .node_id = 0,
 148                         .f0 = PCI_DEV(0, 0x18, 0),
 149                         .f1 = PCI_DEV(0, 0x18, 1),
 150                         .f2 = PCI_DEV(0, 0x18, 2),
 151                         .f3 = PCI_DEV(0, 0x18, 3),
 152                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 153                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 154                 },
 155 #endif
 156 #if SECOND_CPU
 157                 {
 158                         .node_id = 1,
 159                         .f0 = PCI_DEV(0, 0x19, 0),
 160                         .f1 = PCI_DEV(0, 0x19, 1),
 161                         .f2 = PCI_DEV(0, 0x19, 2),
 162                         .f3 = PCI_DEV(0, 0x19, 3),
 163                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 164                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 165                 },
 166 #endif
 167         };
 168
 169         int needs_reset;
 170
 171         if (bist == 0) {
 172                 /* Skip this if there was a built in self test failure */
 173                 amd_early_mtrr_init();
 174                 enable_lapic();
 175                 init_timer();
 176
 177                 if (cpu_init_detected()) {
 178 #if 1
 179                         asm volatile ("jmp __cpu_reset");
 180 #else
 181                 /* cpu reset also reset the memtroller ????
 182                         need soft_reset to reset all except keep HT link freq and width */
 183                         distinguish_cpu_resets();
 184                         soft2_reset();
 185 #endif
 186                 }
 187                 distinguish_cpu_resets();
 188                 if (!boot_cpu()) {
 189                         stop_this_cpu();
 190                 }
 191         }
 192
 193         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 194         uart_init();
 195         console_init();
 196
 197         /* Halt if there was a built in self test failure */
 198         report_bist_failure(bist);
 199
 200         setup_default_resource_map();
 201         needs_reset = setup_coherent_ht_domain();
 202         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 203         if (needs_reset) {
 204                 print_info("ht reset -\r\n");
 205                 soft_reset();
 206         }
 207 #if 0
 208         print_pci_devices();
 209 #endif
 210         enable_smbus();
 211 #if 0
 212 //      dump_spd_registers(&cpu[0]);
 213         dump_smbus_registers();
 214 #endif
 215
 216         memreset_setup();
 217         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 218
 219 #if 0
 220         dump_pci_devices();
 221 #endif
 222 #if 0
 223         dump_pci_device(PCI_DEV(0, 0x18, 1));
 224 #endif
 225
 226         /* Check all of memory */
 227 #if 0
 228         msr_t msr;
 229         msr = rdmsr(TOP_MEM2);
 230         print_debug("TOP_MEM2: ");
 231         print_debug_hex32(msr.hi);
 232         print_debug_hex32(msr.lo);
 233         print_debug("\r\n");
 234 #endif
 235 /*
 236 #if  0
 237         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 238 #else
 239 #if TOTAL_CPUS < 2
 240         // Check 16MB of memory @ 0
 241         ram_check(0x00000000, 0x01000000);
 242 #else
 243         // Check 16MB of memory @ 2GB
 244         ram_check(0x80000000, 0x81000000);
 245 #endif
 246 #endif
 247 */
 248 }