src/mainboard/tyan/s2882/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include <cpu/amd/model_fxx_rev.h>
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27 #include "cpu/amd/dualcore/dualcore.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 /* Look up a which bus a given node/link combination is on.
  32  * return 0 when we can't find the answer.
  33  */
  34 static unsigned node_link_to_bus(unsigned node, unsigned link)
  35 {
  36         unsigned reg;
  37
  38         for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
  39                 unsigned config_map;
  40                 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
  41                 if ((config_map & 3) != 3) {
  42                         continue;
  43                 }
  44                 if ((((config_map >> 4) & 7) == node) &&
  45                         (((config_map >> 8) & 3) == link))
  46                 {
  47                         return (config_map >> 16) & 0xff;
  48                 }
  49         }
  50         return 0;
  51 }
  52
  53 static void hard_reset(void)
  54 {
  55         device_t dev;
  56
  57         /* Find the device */
  58         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
  59
  60         set_bios_reset();
  61
  62         /* enable cf9 */
  63         pci_write_config8(dev, 0x41, 0xf1);
  64         /* reset */
  65         outb(0x0e, 0x0cf9);
  66 }
  67
  68 static void soft_reset(void)
  69 {
  70         device_t dev;
  71
  72         /* Find the device */
  73         dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
  74
  75         set_bios_reset();
  76         pci_write_config8(dev, 0x47, 1);
  77 }
  78
  79 #define REV_B_RESET 0
  80 static void memreset_setup(void)
  81 {
  82    if (is_cpu_pre_c0()) {
  83         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  84    }
  85    else {
  86         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  87    }
  88         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  89 }
  90
  91 static void memreset(int controllers, const struct mem_controller *ctrl)
  92 {
  93    if (is_cpu_pre_c0()) {
  94         udelay(800);
  95         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  96         udelay(90);
  97    }
  98 }
  99
 100 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 101 {
 102         /* nothing to do */
 103 }
 104
 105 static inline int spd_read_byte(unsigned device, unsigned address)
 106 {
 107         return smbus_read_byte(device, address);
 108 }
 109
 110 #include "northbridge/amd/amdk8/setup_resource_map.c"
 111 #define K8_4RANK_DIMM_SUPPORT 1
 112 #include "northbridge/amd/amdk8/raminit.c"
 113 #include "northbridge/amd/amdk8/resourcemap.c"
 114 #include "northbridge/amd/amdk8/coherent_ht.c"
 115 #include "sdram/generic_sdram.c"
 116
 117 #define FIRST_CPU  1
 118 #define SECOND_CPU 1
 119 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 120 static void main(unsigned long bist)
 121 {
 122         /*
 123          * GPIO28 of 8111 will control H0_MEMRESET_L
 124          * GPIO29 of 8111 will control H1_MEMRESET_L
 125          */
 126         static const struct mem_controller cpu[] = {
 127 #if FIRST_CPU
 128                 {
 129                         .node_id = 0,
 130                         .f0 = PCI_DEV(0, 0x18, 0),
 131                         .f1 = PCI_DEV(0, 0x18, 1),
 132                         .f2 = PCI_DEV(0, 0x18, 2),
 133                         .f3 = PCI_DEV(0, 0x18, 3),
 134                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 135                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 136                 },
 137 #endif
 138 #if SECOND_CPU
 139                 {
 140                         .node_id = 1,
 141                         .f0 = PCI_DEV(0, 0x19, 0),
 142                         .f1 = PCI_DEV(0, 0x19, 1),
 143                         .f2 = PCI_DEV(0, 0x19, 2),
 144                         .f3 = PCI_DEV(0, 0x19, 3),
 145                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 146                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 147                 },
 148 #endif
 149         };
 150
 151         int needs_reset;
 152 #if CONFIG_LOGICAL_CPUS==1
 153         struct node_core_id id;
 154 #else
 155         unsigned nodeid;
 156 #endif
 157
 158         if (bist == 0) {
 159                 k8_init_and_stop_secondaries();
 160         }
 161
 162         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 163         uart_init();
 164         console_init();
 165
 166         /* Halt if there was a built in self test failure */
 167 //        report_bist_failure(bist);
 168
 169         setup_default_resource_map();
 170         needs_reset = setup_coherent_ht_domain();
 171         needs_reset |= ht_setup_chains_x();
 172         if (needs_reset) {
 173                 print_info("ht reset -\r\n");
 174                 soft_reset();
 175         }
 176         enable_smbus();
 177
 178         memreset_setup();
 179         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 180
 181 }