2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
50 depends "$(MAINBOARD)/failover.c ./romcc"
51 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
54 makerule ./failover.inc
55 depends "$(MAINBOARD)/failover.c ./romcc"
56 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
60 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
61 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
64 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
65 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
69 ## Build our 16 bit and 32 bit linuxBIOS entry code
71 mainboardinit cpu/x86/16bit/entry16.inc
72 mainboardinit cpu/x86/32bit/entry32.inc
73 ldscript /cpu/x86/16bit/entry16.lds
74 ldscript /cpu/x86/32bit/entry32.lds
77 ## Build our reset vector (This is where linuxBIOS is entered)
80 mainboardinit cpu/x86/16bit/reset16.inc
81 ldscript /cpu/x86/16bit/reset16.lds
83 mainboardinit cpu/x86/32bit/reset32.inc
84 ldscript /cpu/x86/32bit/reset32.lds
87 ### Should this be in the northbridge code?
88 mainboardinit arch/i386/lib/cpu_reset.inc
91 ## Include an id string (For safe flashing)
93 mainboardinit arch/i386/lib/id.inc
94 ldscript /arch/i386/lib/id.lds
97 ### This is the early phase of linuxBIOS startup
98 ### Things are delicate and we test to see if we should
99 ### failover to another image.
101 if USE_FALLBACK_IMAGE
102 ldscript /arch/i386/lib/failover.lds
103 mainboardinit ./failover.inc
107 ### O.k. We aren't just an intermediary anymore!
113 mainboardinit cpu/x86/fpu/enable_fpu.inc
114 mainboardinit cpu/x86/mmx/enable_mmx.inc
115 mainboardinit cpu/x86/sse/enable_sse.inc
116 mainboardinit ./auto.inc
117 mainboardinit cpu/x86/sse/disable_sse.inc
118 mainboardinit cpu/x86/mmx/disable_mmx.inc
121 ## Include the secondary Configuration files
127 # sample config for tyan/s2882
128 chip northbridge/amd/amdk8/root_complex
129 device apic_cluster 0 on
130 chip cpu/amd/socket_940
135 device pci_domain 0 on
136 chip northbridge/amd/amdk8
137 device pci 18.0 on # northbridge
138 # devices on link 0, link 0 == LDT 0
139 chip southbridge/amd/amd8131
140 # the on/off keyword is mandatory
142 chip drivers/pci/onboard
143 device pci 6.0 on end # adaptec
144 device pci 6.1 on end
146 chip drivers/pci/onboard
147 device pci 9.0 on end # broadcom 5704
148 device pci 9.1 on end
151 device pci 0.1 on end
152 device pci 1.0 on end
153 device pci 1.1 on end
155 chip southbridge/amd/amd8111
156 # this "device pci 0.0" is the parent the next one
159 device pci 0.0 on end
160 device pci 0.1 on end
161 device pci 0.2 off end
162 device pci 1.0 off end
163 chip drivers/pci/onboard
164 device pci 5.0 on end
166 # chip drivers/ati/ragexl
167 chip drivers/pci/onboard
168 device pci 6.0 on end
169 register "rom_address" = "0xfff80000"
171 chip drivers/pci/onboard
172 device pci 8.0 on end #intel 10/100
176 chip superio/winbond/w83627hf
177 device pnp 2e.0 on # Floppy
182 device pnp 2e.1 off # Parallel Port
186 device pnp 2e.2 on # Com1
190 device pnp 2e.3 off # Com2
194 device pnp 2e.5 on # Keyboard
200 device pnp 2e.6 off # CIR
203 device pnp 2e.7 off # GAME_MIDI_GIPO1
208 device pnp 2e.8 off end # GPIO2
209 device pnp 2e.9 off end # GPIO3
210 device pnp 2e.a off end # ACPI
211 device pnp 2e.b on # HW Monitor
217 device pci 1.1 on end
218 device pci 1.2 on end
220 # chip drivers/generic/generic #dimm 0-0-0
221 # device i2c 50 on end
223 # chip drivers/generic/generic #dimm 0-0-1
224 # device i2c 51 on end
226 # chip drivers/generic/generic #dimm 0-1-0
227 # device i2c 52 on end
229 # chip drivers/generic/generic #dimm 0-1-1
230 # device i2c 53 on end
232 # chip drivers/generic/generic #dimm 1-0-0
233 # device i2c 54 on end
235 # chip drivers/generic/generic #dimm 1-0-1
236 # device i2c 55 on end
238 # chip drivers/generic/generic #dimm 1-1-0
239 # device i2c 56 on end
241 # chip drivers/generic/generic #dimm 1-1-1
242 # device i2c 57 on end
245 device pci 1.5 off end
246 device pci 1.6 off end
247 register "ide0_enable" = "1"
248 register "ide1_enable" = "1"
250 end # device pci 18.0
252 device pci 18.0 on end
253 device pci 18.0 on end
255 device pci 18.1 on end
256 device pci 18.2 on end
257 device pci 18.3 on end