2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The coreboot bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of coreboot will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up coreboot,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
45 if HAVE_MP_TABLE object mptable.o end
46 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
52 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
60 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
61 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
66 ## Build our 16 bit and 32 bit coreboot entry code
69 mainboardinit cpu/x86/16bit/entry16.inc
70 ldscript /cpu/x86/16bit/entry16.lds
73 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/32bit/entry32.lds
80 ldscript /cpu/amd/car/cache_as_ram.lds
84 ## Build our reset vector (This is where coreboot is entered)
87 mainboardinit cpu/x86/16bit/reset16.inc
88 ldscript /cpu/x86/16bit/reset16.lds
90 mainboardinit cpu/x86/32bit/reset32.inc
91 ldscript /cpu/x86/32bit/reset32.lds
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
101 ## Setup Cache-As-Ram
103 mainboardinit cpu/amd/car/cache_as_ram.inc
106 ### This is the early phase of coreboot startup
107 ### Things are delicate and we test to see if we should
108 ### failover to another image.
110 if USE_FALLBACK_IMAGE
111 ldscript /arch/i386/lib/failover.lds
115 ### O.k. We aren't just an intermediary anymore!
124 mainboardinit ./auto.inc
128 ## Include the secondary Configuration files
132 # sample config for tyan/s2882
133 chip northbridge/amd/amdk8/root_complex
134 device apic_cluster 0 on
135 chip cpu/amd/socket_940
140 device pci_domain 0 on
141 chip northbridge/amd/amdk8
142 device pci 18.0 on # northbridge
143 # devices on link 0, link 0 == LDT 0
144 chip southbridge/amd/amd8131
145 # the on/off keyword is mandatory
147 chip drivers/pci/onboard
148 device pci 6.0 on end # adaptec
149 device pci 6.1 on end
151 chip drivers/pci/onboard
152 device pci 9.0 on end # broadcom 5704
153 device pci 9.1 on end
156 device pci 0.1 on end
157 device pci 1.0 on end
158 device pci 1.1 on end
160 chip southbridge/amd/amd8111
161 # this "device pci 0.0" is the parent the next one
164 device pci 0.0 on end
165 device pci 0.1 on end
166 device pci 0.2 off end
167 device pci 1.0 off end
168 chip drivers/pci/onboard
169 device pci 5.0 on end
171 # chip drivers/ati/ragexl
172 chip drivers/pci/onboard
173 device pci 6.0 on end
174 register "rom_address" = "0xfff00000"
176 chip drivers/pci/onboard
177 device pci 8.0 on end #intel 10/100
181 chip superio/winbond/w83627hf
182 device pnp 2e.0 on # Floppy
187 device pnp 2e.1 off # Parallel Port
191 device pnp 2e.2 on # Com1
195 device pnp 2e.3 off # Com2
199 device pnp 2e.5 on # Keyboard
205 device pnp 2e.6 off # CIR
208 device pnp 2e.7 off # GAME_MIDI_GIPO1
213 device pnp 2e.8 off end # GPIO2
214 device pnp 2e.9 off end # GPIO3
215 device pnp 2e.a off end # ACPI
216 device pnp 2e.b on # HW Monitor
222 device pci 1.1 on end
223 device pci 1.2 on end
224 device pci 1.3 on end
226 # chip drivers/generic/generic #dimm 0-0-0
227 # device i2c 50 on end
229 # chip drivers/generic/generic #dimm 0-0-1
230 # device i2c 51 on end
232 # chip drivers/generic/generic #dimm 0-1-0
233 # device i2c 52 on end
235 # chip drivers/generic/generic #dimm 0-1-1
236 # device i2c 53 on end
238 # chip drivers/generic/generic #dimm 1-0-0
239 # device i2c 54 on end
241 # chip drivers/generic/generic #dimm 1-0-1
242 # device i2c 55 on end
244 # chip drivers/generic/generic #dimm 1-1-0
245 # device i2c 56 on end
247 # chip drivers/generic/generic #dimm 1-1-1
248 # device i2c 57 on end
251 device pci 1.5 off end
252 device pci 1.6 off end
253 register "ide0_enable" = "1"
254 register "ide1_enable" = "1"
256 end # device pci 18.0
258 device pci 18.0 on end
259 device pci 18.0 on end
261 device pci 18.1 on end
262 device pci 18.2 on end
263 device pci 18.3 on end