src/mainboard/tyan/s2882/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12 #
  13 #
  14 ###
  15 ### Set all of the defaults for an x86 architecture
  16 ###
  17 #
  18 #
  19 ###
  20 ### Build the objects we have code for in this directory.
  21 ###
  22 ##object mainboard.o
  23 config chip.h
  24 register "fixup_scsi" = "1"
  25 register "fixup_vga" = "1"
  26
  27
  28 ##
  29 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  30 ##
  31 default LB_CKS_RANGE_START=49
  32 default LB_CKS_RANGE_END=122
  33 default LB_CKS_LOC=123
  34
  35 driver mainboard.o
  36 #driver adaptec_scsi.o
  37 #driver si_sata.o
  38 #driver intel_nic.o
  39 #driver broadcom_nic.o
  40 #object reset.o
  41 if HAVE_MP_TABLE object mptable.o end
  42 if HAVE_PIRQ_TABLE object irq_tables.o end
  43 #
  44 default HARD_RESET_BUS=1
  45 default HARD_RESET_DEVICE=4
  46 default HARD_RESET_FUNCTION=0
  47 #
  48 arch i386 end
  49 #cpu k8 end
  50 #
  51 ###
  52 ### Build our 16 bit and 32 bit linuxBIOS entry code
  53 ###
  54 mainboardinit cpu/i386/entry16.inc
  55 mainboardinit cpu/i386/entry32.inc
  56 mainboardinit cpu/i386/bist32.inc
  57 ldscript /cpu/i386/entry16.lds
  58 ldscript /cpu/i386/entry32.lds
  59 #
  60 ###
  61 ### Build our reset vector (This is where linuxBIOS is entered)
  62 ###
  63 if USE_FALLBACK_IMAGE
  64         mainboardinit cpu/i386/reset16.inc
  65         ldscript /cpu/i386/reset16.lds
  66 else
  67         mainboardinit cpu/i386/reset32.inc
  68         ldscript /cpu/i386/reset32.lds
  69 end
  70 #
  71 #### Should this be in the northbridge code?
  72 mainboardinit arch/i386/lib/cpu_reset.inc
  73 #
  74 ###
  75 ### Include an id string (For safe flashing)
  76 ###
  77 mainboardinit arch/i386/lib/id.inc
  78 ldscript /arch/i386/lib/id.lds
  79 #
  80 ####
  81 #### This is the early phase of linuxBIOS startup
  82 #### Things are delicate and we test to see if we should
  83 #### failover to another image.
  84 ####
  85 #option MAX_REBOOT_CNT=2
  86 if USE_FALLBACK_IMAGE
  87   ldscript /arch/i386/lib/failover.lds
  88 end
  89 #
  90 ###
  91 ### Setup our mtrrs
  92 ###
  93 mainboardinit cpu/k8/earlymtrr.inc
  94 ###
  95 ### Only the bootstrap cpu makes it here.
  96 ### Failover if we need to
  97 ###
  98 #
  99 if USE_FALLBACK_IMAGE
 100   mainboardinit ./failover.inc
 101 end
 102
 103 #
 104 #
 105 ###
 106 ### Setup the serial port
 107 ###
 108 mainboardinit pc80/serial.inc
 109 mainboardinit arch/i386/lib/console.inc
 110 mainboardinit cpu/i386/bist32_fail.inc
 111 #
 112 ####
 113 #### O.k. We aren't just an intermediary anymore!
 114 ####
 115 #
 116 ###
 117 ### When debugging disable the watchdog timer
 118 ###
 119 ##option MAXIMUM_CONSOLE_LOGLEVEL=7
 120 #default MAXIMUM_CONSOLE_LOGLEVEL=7
 121 #
 122 #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
 123 #
 124 ###
 125 ### Romcc output
 126 ###
 127
 128 makerule ./failover.E
 129         depends "$(MAINBOARD)/failover.c"
 130         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 131 end
 132
 133 makerule ./failover.inc
 134         depends "./romcc ./failover.E"
 135         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
 136 end
 137
 138 makerule ./auto.E
 139         depends "$(MAINBOARD)/auto.c option_table.h"
 140         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 141 end
 142 makerule ./auto.inc
 143         depends "./romcc ./auto.E"
 144         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 145 end
 146 mainboardinit cpu/k8/enable_mmx_sse.inc
 147 mainboardinit ./auto.inc
 148 mainboardinit cpu/k8/disable_mmx_sse.inc
 149 #
 150 ###
 151 ### Include the secondary Configuration files
 152 ###
 153
 154 northbridge amd/amdk8 "mc0"
 155         pci 0:18.0
 156         pci 0:18.0
 157         pci 0:18.0
 158         pci 0:18.1
 159         pci 0:18.2
 160         pci 0:18.3
 161         southbridge amd/amd8131 "amd8131" link 0
 162                 pci 0:0.0
 163                 pci 0:0.1
 164                 pci 0:1.0
 165                 pci 0:1.1
 166         end
 167         southbridge amd/amd8111 "amd8111" link 0
 168                 pci 0:0.0
 169                 pci 0:1.0 on
 170                 pci 0:1.1 on
 171                 pci 0:1.2 on
 172                 pci 0:1.3 on
 173                 pci 0:1.5 off
 174                 pci 0:1.6 off
 175                 pci 1:0.0 on
 176                 pci 1:0.1 on
 177                 pci 1:0.2 on
 178                 pci 1:1.0 off
 179                 superio winbond/w83627hf link 1
 180                         pnp 2e.0 on #  Floppy
 181                                  io 0x60 = 0x3f0
 182                                 irq 0x70 = 6
 183                                 drq 0x74 = 2
 184                         pnp 2e.1 off #  Parallel Port
 185                                  io 0x60 = 0x378
 186                                 irq 0x70 = 7
 187                         pnp 2e.2 on #  Com1
 188                                  io 0x60 = 0x3f8
 189                                 irq 0x70 = 4
 190                         pnp 2e.3 off #  Com2
 191                                  io 0x60 = 0x2f8
 192                                 irq 0x70 = 3
 193                         pnp 2e.5 on #  Keyboard
 194                                  io 0x60 = 0x60
 195                                  io 0x62 = 0x64
 196                                 irq 0x70 = 1
 197                                 irq 0x72 = 12
 198                         pnp 2e.6 off #  CIR
 199                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 200                         pnp 2e.8 off #  GPIO2
 201                         pnp 2e.9 off #  GPIO3
 202                         pnp 2e.a off #  ACPI
 203                         pnp 2e.b on  #  HW Monitor
 204                                  io 0x60 = 0x290
 205                 end
 206         end
 207 end
 208
 209 northbridge amd/amdk8 "mc1"
 210         pci 0:19.0
 211         pci 0:19.0
 212         pci 0:19.0
 213         pci 0:19.1
 214         pci 0:19.2
 215         pci 0:19.3
 216 end
 217
 218 dir /pc80
 219 #dir /bioscall
 220 cpu k8 "cpu0"
 221   register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 222 end
 223
 224 cpu k8 "cpu1"
 225 end