2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
45 if HAVE_MP_TABLE object mptable.o end
46 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
55 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
61 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
62 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
63 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
64 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
74 depends "$(MAINBOARD)/failover.c ./romcc"
75 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
78 makerule ./failover.inc
79 depends "$(MAINBOARD)/failover.c ./romcc"
80 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
84 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
85 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
88 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
89 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
94 ## Build our 16 bit and 32 bit linuxBIOS entry code
96 mainboardinit cpu/x86/16bit/entry16.inc
97 mainboardinit cpu/x86/32bit/entry32.inc
98 ldscript /cpu/x86/16bit/entry16.lds
101 ldscript /cpu/x86/32bit/entry32.lds
105 ldscript /cpu/amd/car/cache_as_ram.lds
110 ## Build our reset vector (This is where linuxBIOS is entered)
112 if USE_FALLBACK_IMAGE
113 mainboardinit cpu/x86/16bit/reset16.inc
114 ldscript /cpu/x86/16bit/reset16.lds
116 mainboardinit cpu/x86/32bit/reset32.inc
117 ldscript /cpu/x86/32bit/reset32.lds
122 ### Should this be in the northbridge code?
123 mainboardinit arch/i386/lib/cpu_reset.inc
127 ## Include an id string (For safe flashing)
129 mainboardinit arch/i386/lib/id.inc
130 ldscript /arch/i386/lib/id.lds
134 ## Setup Cache-As-Ram
136 mainboardinit cpu/amd/car/cache_as_ram.inc
140 ### This is the early phase of linuxBIOS startup
141 ### Things are delicate and we test to see if we should
142 ### failover to another image.
144 if USE_FALLBACK_IMAGE
146 ldscript /arch/i386/lib/failover.lds
148 ldscript /arch/i386/lib/failover.lds
149 mainboardinit ./failover.inc
154 ### O.k. We aren't just an intermediary anymore!
165 mainboardinit ./auto.inc
173 mainboardinit cpu/x86/fpu/enable_fpu.inc
174 mainboardinit cpu/x86/mmx/enable_mmx.inc
175 mainboardinit cpu/x86/sse/enable_sse.inc
176 mainboardinit ./auto.inc
177 mainboardinit cpu/x86/sse/disable_sse.inc
178 mainboardinit cpu/x86/mmx/disable_mmx.inc
183 ## Include the secondary Configuration files
189 # sample config for tyan/s2882
190 chip northbridge/amd/amdk8/root_complex
191 device apic_cluster 0 on
192 chip cpu/amd/socket_940
197 device pci_domain 0 on
198 chip northbridge/amd/amdk8
199 device pci 18.0 on # northbridge
200 # devices on link 0, link 0 == LDT 0
201 chip southbridge/amd/amd8131
202 # the on/off keyword is mandatory
204 chip drivers/pci/onboard
205 device pci 6.0 on end # adaptec
206 device pci 6.1 on end
208 chip drivers/pci/onboard
209 device pci 9.0 on end # broadcom 5704
210 device pci 9.1 on end
213 device pci 0.1 on end
214 device pci 1.0 on end
215 device pci 1.1 on end
217 chip southbridge/amd/amd8111
218 # this "device pci 0.0" is the parent the next one
221 device pci 0.0 on end
222 device pci 0.1 on end
223 device pci 0.2 off end
224 device pci 1.0 off end
225 chip drivers/pci/onboard
226 device pci 5.0 on end
228 # chip drivers/ati/ragexl
229 chip drivers/pci/onboard
230 device pci 6.0 on end
231 register "rom_address" = "0xfff80000"
233 chip drivers/pci/onboard
234 device pci 8.0 on end #intel 10/100
238 chip superio/winbond/w83627hf
239 device pnp 2e.0 on # Floppy
244 device pnp 2e.1 off # Parallel Port
248 device pnp 2e.2 on # Com1
252 device pnp 2e.3 off # Com2
256 device pnp 2e.5 on # Keyboard
262 device pnp 2e.6 off # CIR
265 device pnp 2e.7 off # GAME_MIDI_GIPO1
270 device pnp 2e.8 off end # GPIO2
271 device pnp 2e.9 off end # GPIO3
272 device pnp 2e.a off end # ACPI
273 device pnp 2e.b on # HW Monitor
279 device pci 1.1 on end
280 device pci 1.2 on end
281 device pci 1.3 on end
283 # chip drivers/generic/generic #dimm 0-0-0
284 # device i2c 50 on end
286 # chip drivers/generic/generic #dimm 0-0-1
287 # device i2c 51 on end
289 # chip drivers/generic/generic #dimm 0-1-0
290 # device i2c 52 on end
292 # chip drivers/generic/generic #dimm 0-1-1
293 # device i2c 53 on end
295 # chip drivers/generic/generic #dimm 1-0-0
296 # device i2c 54 on end
298 # chip drivers/generic/generic #dimm 1-0-1
299 # device i2c 55 on end
301 # chip drivers/generic/generic #dimm 1-1-0
302 # device i2c 56 on end
304 # chip drivers/generic/generic #dimm 1-1-1
305 # device i2c 57 on end
308 device pci 1.5 off end
309 device pci 1.6 off end
310 register "ide0_enable" = "1"
311 register "ide1_enable" = "1"
313 end # device pci 18.0
315 device pci 18.0 on end
316 device pci 18.0 on end
318 device pci 18.1 on end
319 device pci 18.2 on end
320 device pci 18.3 on end