src/mainboard/tyan/s2881/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include "option_table.h"
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "console/console.c"
  18 #include "lib/ramtest.c"
  19
  20 #include <cpu/amd/model_fxx_rev.h>
  21
  22 #include "northbridge/amd/amdk8/incoherent_ht.c"
  23 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  24 #include "northbridge/amd/amdk8/raminit.h"
  25 #include "cpu/amd/model_fxx/apic_timer.c"
  26 #include "lib/delay.c"
  27
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30 #include "northbridge/amd/amdk8/debug.c"
  31 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  32
  33 #include "cpu/x86/mtrr/earlymtrr.c"
  34 #include "cpu/x86/bist.h"
  35
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  41
  42 static void memreset_setup(void)
  43 {
  44    if (is_cpu_pre_c0()) {
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  46    }
  47    else {
  48         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  49    }
  50         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  51 }
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55    if (is_cpu_pre_c0()) {
  56         udelay(800);
  57         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  58         udelay(90);
  59    }
  60 }
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66
  67 static inline int spd_read_byte(unsigned device, unsigned address)
  68 {
  69         return smbus_read_byte(device, address);
  70 }
  71
  72 #include "northbridge/amd/amdk8/raminit.c"
  73 #include "resourcemap.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76
  77 #include "cpu/amd/dualcore/dualcore.c"
  78
  79
  80
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84
  85 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  86 #include "northbridge/amd/amdk8/early_ht.c"
  87
  88 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  89 {
  90         static const uint16_t spd_addr [] = {
  91                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  92                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  93 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  94                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  95                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  96 #endif
  97         };
  98
  99         int needs_reset;
 100         unsigned bsp_apicid = 0;
 101
 102         struct mem_controller ctrl[8];
 103         unsigned nodes;
 104
 105         if (!cpu_init_detectedx && boot_cpu()) {
 106                 /* Nothing special needs to be done to find bus 0 */
 107                 /* Allow the HT devices to be found */
 108
 109                 enumerate_ht_chain();
 110
 111                 /* Setup the amd8111 */
 112                 amd8111_enable_rom();
 113         }
 114
 115         if (bist == 0) {
 116                 bsp_apicid = init_cpus(cpu_init_detectedx);
 117         }
 118
 119 //      post_code(0x32);
 120
 121         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 122         uart_init();
 123         console_init();
 124
 125         /* Halt if there was a built in self test failure */
 126         report_bist_failure(bist);
 127
 128         setup_s2881_resource_map();
 129 #if 0
 130         dump_pci_device(PCI_DEV(0, 0x18, 0));
 131         dump_pci_device(PCI_DEV(0, 0x19, 0));
 132 #endif
 133
 134         needs_reset = setup_coherent_ht_domain();
 135
 136         wait_all_core0_started();
 137 #if CONFIG_LOGICAL_CPUS==1
 138         // It is said that we should start core1 after all core0 launched
 139         start_other_cores();
 140         wait_all_other_cores_started(bsp_apicid);
 141 #endif
 142
 143         needs_reset |= ht_setup_chains_x();
 144
 145         if (needs_reset) {
 146                 print_info("ht reset -\n");
 147                 soft_reset();
 148         }
 149
 150         enable_smbus();
 151 #if 0
 152         dump_spd_registers(&cpu[0]);
 153 #endif
 154 #if 0
 155         dump_smbus_registers();
 156 #endif
 157
 158         allow_all_aps_stop(bsp_apicid);
 159
 160         nodes = get_nodes();
 161         //It's the time to set ctrl now;
 162         fill_mem_ctrl(nodes, ctrl, spd_addr);
 163
 164         memreset_setup();
 165         sdram_initialize(nodes, ctrl);
 166
 167 #if 0
 168         dump_pci_devices();
 169 #endif
 170
 171         post_cache_as_ram();
 172 }
 173