src/mainboard/tyan/s2881/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #define SET_NB_CFG_54 1
   8 #endif
   9
  10 #include <stdint.h>
  11 #include <string.h>
  12 #include <device/pci_def.h>
  13 #include <arch/io.h>
  14 #include <device/pnp_def.h>
  15 #include <arch/romcc_io.h>
  16 #include <cpu/x86/lapic.h>
  17 #include "option_table.h"
  18 #include "pc80/mc146818rtc_early.c"
  19 #include "pc80/serial.c"
  20 #include "arch/i386/lib/console.c"
  21 #include "lib/ramtest.c"
  22
  23 #if 0
  24 static void post_code(uint8_t value) {
  25 #if 1
  26         int i;
  27         for(i=0;i<0x80000;i++) {
  28                 outb(value, 0x80);
  29         }
  30 #endif
  31 }
  32 #endif
  33
  34 #include <cpu/amd/model_fxx_rev.h>
  35
  36 #include "northbridge/amd/amdk8/incoherent_ht.c"
  37 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  38 #include "northbridge/amd/amdk8/raminit.h"
  39 #include "cpu/amd/model_fxx/apic_timer.c"
  40 #include "lib/delay.c"
  41
  42 #include "cpu/x86/lapic/boot_cpu.c"
  43 #include "northbridge/amd/amdk8/reset_test.c"
  44 #include "northbridge/amd/amdk8/debug.c"
  45 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  46
  47 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  48 #include "cpu/x86/bist.h"
  49
  50 #include "northbridge/amd/amdk8/setup_resource_map.c"
  51
  52 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  53
  54 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  55
  56 static void memreset_setup(void)
  57 {
  58    if (is_cpu_pre_c0()) {
  59         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  60    }
  61    else {
  62         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  63    }
  64         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  65 }
  66
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69    if (is_cpu_pre_c0()) {
  70         udelay(800);
  71         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  72         udelay(90);
  73    }
  74 }
  75
  76 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  77 {
  78         /* nothing to do */
  79 }
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86
  87 #include "northbridge/amd/amdk8/raminit.c"
  88 #include "resourcemap.c"
  89 #include "northbridge/amd/amdk8/coherent_ht.c"
  90 #include "lib/generic_sdram.c"
  91
  92 #include "cpu/amd/dualcore/dualcore.c"
  93
  94
  95 #include "cpu/amd/car/copy_and_run.c"
  96
  97 #include "cpu/amd/car/post_cache_as_ram.c"
  98
  99 #include "cpu/amd/model_fxx/init_cpus.c"
 100
 101
 102 #if CONFIG_USE_FALLBACK_IMAGE == 1
 103
 104 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 105 #include "northbridge/amd/amdk8/early_ht.c"
 106
 107 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 108 {
 109         unsigned last_boot_normal_x = last_boot_normal();
 110
 111         /* Is this a cpu only reset? or Is this a secondary cpu? */
 112         if ((cpu_init_detectedx) || (!boot_cpu())) {
 113                 if (last_boot_normal_x) {
 114                         goto normal_image;
 115                 } else {
 116                         goto fallback_image;
 117                 }
 118         }
 119
 120         /* Nothing special needs to be done to find bus 0 */
 121         /* Allow the HT devices to be found */
 122
 123         enumerate_ht_chain();
 124
 125         /* Setup the amd8111 */
 126         amd8111_enable_rom();
 127
 128         /* Is this a deliberate reset by the bios */
 129 //        post_code(0x22);
 130         if (bios_reset_detected() && last_boot_normal_x) {
 131                 goto normal_image;
 132         }
 133         /* This is the primary cpu how should I boot? */
 134         else if (do_normal_boot()) {
 135                 goto normal_image;
 136         }
 137         else {
 138                 goto fallback_image;
 139         }
 140  normal_image:
 141 //        post_code(0x23);
 142         __asm__ volatile ("jmp __normal_image"
 143                 : /* outputs */
 144                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 145                 );
 146
 147  fallback_image:
 148 //        post_code(0x25);
 149         ;
 150 }
 151 #endif
 152
 153 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 154
 155 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 156 {
 157
 158 #if CONFIG_USE_FALLBACK_IMAGE == 1
 159         failover_process(bist, cpu_init_detectedx);
 160 #endif
 161         real_main(bist, cpu_init_detectedx);
 162
 163 }
 164
 165 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 166 {
 167         static const uint16_t spd_addr [] = {
 168                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 169                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 170 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 171                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 172                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 173 #endif
 174         };
 175
 176         int needs_reset;
 177         unsigned bsp_apicid = 0;
 178
 179         struct mem_controller ctrl[8];
 180         unsigned nodes;
 181
 182         if (bist == 0) {
 183                 bsp_apicid = init_cpus(cpu_init_detectedx);
 184         }
 185
 186 //      post_code(0x32);
 187
 188         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 189         uart_init();
 190         console_init();
 191
 192         /* Halt if there was a built in self test failure */
 193         report_bist_failure(bist);
 194
 195         setup_s2881_resource_map();
 196 #if 0
 197         dump_pci_device(PCI_DEV(0, 0x18, 0));
 198         dump_pci_device(PCI_DEV(0, 0x19, 0));
 199 #endif
 200
 201         needs_reset = setup_coherent_ht_domain();
 202
 203         wait_all_core0_started();
 204 #if CONFIG_LOGICAL_CPUS==1
 205         // It is said that we should start core1 after all core0 launched
 206         start_other_cores();
 207         wait_all_other_cores_started(bsp_apicid);
 208 #endif
 209
 210         needs_reset |= ht_setup_chains_x();
 211
 212         if (needs_reset) {
 213                 print_info("ht reset -\r\n");
 214                 soft_reset();
 215         }
 216
 217         enable_smbus();
 218 #if 0
 219         dump_spd_registers(&cpu[0]);
 220 #endif
 221 #if 0
 222         dump_smbus_registers();
 223 #endif
 224
 225         allow_all_aps_stop(bsp_apicid);
 226
 227         nodes = get_nodes();
 228         //It's the time to set ctrl now;
 229         fill_mem_ctrl(nodes, ctrl, spd_addr);
 230
 231         memreset_setup();
 232         sdram_initialize(nodes, ctrl);
 233
 234 #if 0
 235         dump_pci_devices();
 236 #endif
 237
 238         post_cache_as_ram();
 239 }