src/mainboard/tyan/s2881/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <lib.h>
  11 #include <spd.h>
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "superio/winbond/w83627hf/early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25 #include "southbridge/amd/amd8111/early_ctrl.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void memreset_setup(void)
  30 {
  31    if (is_cpu_pre_c0())
  32         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  33    else
  34         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  35    outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  36 }
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40    if (is_cpu_pre_c0()) {
  41         udelay(800);
  42         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  43         udelay(90);
  44    }
  45 }
  46
  47 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  48
  49 static inline int spd_read_byte(unsigned device, unsigned address)
  50 {
  51         return smbus_read_byte(device, address);
  52 }
  53
  54 #include "northbridge/amd/amdk8/raminit.c"
  55 #include "resourcemap.c"
  56 #include "northbridge/amd/amdk8/coherent_ht.c"
  57 #include "lib/generic_sdram.c"
  58 #include "cpu/amd/dualcore/dualcore.c"
  59 #include "cpu/amd/car/post_cache_as_ram.c"
  60 #include "cpu/amd/model_fxx/init_cpus.c"
  61 #include "northbridge/amd/amdk8/early_ht.c"
  62
  63 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  64 {
  65         static const uint16_t spd_addr [] = {
  66                 DIMM0, DIMM2, 0, 0,
  67                 DIMM1, DIMM3, 0, 0,
  68 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  69                 DIMM4, DIMM6, 0, 0,
  70                 DIMM5, DIMM7, 0, 0,
  71 #endif
  72         };
  73
  74         int needs_reset;
  75         unsigned bsp_apicid = 0, nodes;
  76         struct mem_controller ctrl[8];
  77
  78         if (!cpu_init_detectedx && boot_cpu()) {
  79                 /* Nothing special needs to be done to find bus 0 */
  80                 /* Allow the HT devices to be found */
  81                 enumerate_ht_chain();
  82         }
  83
  84         if (bist == 0)
  85                 bsp_apicid = init_cpus(cpu_init_detectedx);
  86
  87 //      post_code(0x32);
  88
  89         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  90         uart_init();
  91         console_init();
  92
  93         /* Halt if there was a built in self test failure */
  94         report_bist_failure(bist);
  95
  96         setup_s2881_resource_map();
  97 #if 0
  98         dump_pci_device(PCI_DEV(0, 0x18, 0));
  99         dump_pci_device(PCI_DEV(0, 0x19, 0));
 100 #endif
 101
 102         needs_reset = setup_coherent_ht_domain();
 103
 104         wait_all_core0_started();
 105 #if CONFIG_LOGICAL_CPUS==1
 106         // It is said that we should start core1 after all core0 launched
 107         start_other_cores();
 108         wait_all_other_cores_started(bsp_apicid);
 109 #endif
 110
 111         needs_reset |= ht_setup_chains_x();
 112
 113         if (needs_reset) {
 114                 print_info("ht reset -\n");
 115                 soft_reset();
 116         }
 117
 118         enable_smbus();
 119 #if 0
 120         dump_spd_registers(&cpu[0]);
 121         dump_smbus_registers();
 122 #endif
 123
 124         allow_all_aps_stop(bsp_apicid);
 125
 126         nodes = get_nodes();
 127         //It's the time to set ctrl now;
 128         fill_mem_ctrl(nodes, ctrl, spd_addr);
 129
 130         memreset_setup();
 131         sdram_initialize(nodes, ctrl);
 132
 133 #if 0
 134         dump_pci_devices();
 135 #endif
 136
 137         post_cache_as_ram();
 138 }