1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 void *smp_write_config_table(void *v, unsigned long * processor_map)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "TYAN ";
11 static const char productid[12] = "S2881 ";
12 struct mp_config_table *mc;
14 unsigned char bus_num;
15 unsigned char bus_isa;
16 unsigned char bus_8131_1;
17 unsigned char bus_8131_2;
18 unsigned char bus_8111_1;
20 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
21 memset(mc, 0, sizeof(*mc));
23 memcpy(mc->mpc_signature, sig, sizeof(sig));
24 mc->mpc_length = sizeof(*mc); /* initially just the header */
26 mc->mpc_checksum = 0; /* not yet computed */
27 memcpy(mc->mpc_oem, oem, sizeof(oem));
28 memcpy(mc->mpc_productid, productid, sizeof(productid));
31 mc->mpc_entry_count = 0; /* No entries yet... */
32 mc->mpc_lapic = LAPIC_ADDR;
37 smp_write_processors(mc, processor_map);
44 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
46 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
47 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
51 printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
57 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
59 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
63 printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
68 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
70 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
74 printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
81 /* define bus and isa numbers */
82 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
83 smp_write_bus(mc, bus_num, "PCI ");
85 smp_write_bus(mc, bus_isa, "ISA ");
88 /*I/O APICs: APIC ID Version State Address*/
89 smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
93 dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
95 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
96 base &= PCI_BASE_ADDRESS_MEM_MASK;
97 smp_write_ioapic(mc, 3, 0x11, base);
99 dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
101 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
102 base &= PCI_BASE_ADDRESS_MEM_MASK;
103 smp_write_ioapic(mc, 4, 0x11, base);
107 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
108 */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, 0x2, 0x13);
124 //On Board AMD USB ???
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
127 //On Board ATI Display Adapter
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x2, 0x12);
130 //On Board SI Serial ATA
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x2, 0x11);
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, 0x3, 0x3);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, 0x3, 0x0);
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, 0x3, 0x1);//
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, 0x3, 0x2);//
140 //On Board NIC and LSI scsi
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x3, 0x1);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, 0x3, 0x0);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, 0x3, 0x1);
146 //Slot 1 PCI-X 133/100/66
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
153 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
154 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
155 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
156 /* There is no extension information... */
158 /* Compute the checksums */
159 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
160 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
161 printk_debug("Wrote the mp table end at: %p - %p\n",
162 mc, smp_next_mpe_entry(mc));
163 return smp_next_mpe_entry(mc);
166 unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
169 v = smp_write_floating_table(addr);
170 return (unsigned long)smp_write_config_table(v, processor_map);