1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #if CONFIG_LOGICAL_CPUS==1
7 #include <cpu/amd/dualcore.h>
11 static unsigned node_link_to_bus(unsigned node, unsigned link)
16 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
20 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
25 config_map = pci_read_config32(dev, reg);
26 if ((config_map & 3) != 3) {
29 dst_node = (config_map >> 4) & 7;
30 dst_link = (config_map >> 8) & 3;
31 bus_base = (config_map >> 16) & 0xff;
33 printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
34 dst_node, dst_link, bus_base,
37 if ((dst_node == node) && (dst_link == link))
45 void *smp_write_config_table(void *v)
47 static const char sig[4] = "PCMP";
48 static const char oem[8] = "TYAN ";
49 static const char productid[12] = "S2881 ";
50 struct mp_config_table *mc;
52 unsigned char bus_num;
53 unsigned char bus_isa;
54 unsigned char bus_chain_0;
55 unsigned char bus_8131_1;
56 unsigned char bus_8131_2;
57 unsigned char bus_8111_1;
60 unsigned apicid_8131_1;
61 unsigned apicid_8131_2;
63 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
64 memset(mc, 0, sizeof(*mc));
66 memcpy(mc->mpc_signature, sig, sizeof(sig));
67 mc->mpc_length = sizeof(*mc); /* initially just the header */
69 mc->mpc_checksum = 0; /* not yet computed */
70 memcpy(mc->mpc_oem, oem, sizeof(oem));
71 memcpy(mc->mpc_productid, productid, sizeof(productid));
74 mc->mpc_entry_count = 0; /* No entries yet... */
75 mc->mpc_lapic = LAPIC_ADDR;
80 smp_write_processors(mc);
87 bus_chain_0 = node_link_to_bus(0, 2);
88 if (bus_chain_0 == 0) {
89 printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
94 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
96 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
97 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
101 printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
107 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
109 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
113 printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
118 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
120 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
124 printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
131 /* define bus and isa numbers */
132 for (bus_num = 0; bus_num < bus_isa; bus_num++) {
133 smp_write_bus(mc, bus_num, "PCI ");
135 smp_write_bus(mc, bus_isa, "ISA ");
138 /*I/O APICs: APIC ID Version State Address*/
139 #if CONFIG_LOGICAL_CPUS
140 apicid_base = get_apicid_base(3);
142 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
144 apicid_8111 = apicid_base+0;
145 apicid_8131_1 = apicid_base+1;
146 apicid_8131_2 = apicid_base+2;
148 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
151 struct resource *res;
152 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
154 res = find_resource(dev, PCI_BASE_ADDRESS_0);
156 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
159 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
161 res = find_resource(dev, PCI_BASE_ADDRESS_0);
163 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
169 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
170 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7);
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8);
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc);
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd);
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
183 /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
187 //On Board AMD USB ???
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
190 //On Board ATI Display Adapter
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
193 //On Board SI Serial ATA
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3);
198 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0);
199 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);
202 //On Board NIC and adaptec scsi
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
204 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
205 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x0);
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x1);
208 //Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
210 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2);
212 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3);
214 //Slot 1 PCI-X 133/100/66, Side 2 on raiser card
216 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x1);
217 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x2);
218 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x3);
219 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x0);
221 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
222 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
223 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
224 /* There is no extension information... */
226 /* Compute the checksums */
227 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
228 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
229 printk_debug("Wrote the mp table end at: %p - %p\n",
230 mc, smp_next_mpe_entry(mc));
231 return smp_next_mpe_entry(mc);
234 unsigned long write_smp_table(unsigned long addr)
237 v = smp_write_floating_table(addr);
238 return (unsigned long)smp_write_config_table(v);