src/mainboard/tyan/s2881/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define K8_4RANK_DIMM_SUPPORT 1
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #define SET_NB_CFG_54 1
   8 #endif
   9
  10 #include <stdint.h>
  11 #include <device/pci_def.h>
  12 #include <arch/io.h>
  13 #include <device/pnp_def.h>
  14 #include <arch/romcc_io.h>
  15 #include <cpu/x86/lapic.h>
  16 #include "option_table.h"
  17 #include "pc80/mc146818rtc_early.c"
  18 #include "pc80/serial.c"
  19 #include "arch/i386/lib/console.c"
  20 #include "ram/ramtest.c"
  21
  22 #include <cpu/amd/model_fxx_rev.h>
  23 #include "northbridge/amd/amdk8/incoherent_ht.c"
  24 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  25 #include "northbridge/amd/amdk8/raminit.h"
  26 #include "cpu/amd/model_fxx/apic_timer.c"
  27 #include "lib/delay.c"
  28
  29 #if CONFIG_USE_INIT == 0
  30 #include "lib/memcpy.c"
  31 #endif
  32
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "northbridge/amd/amdk8/debug.c"
  36 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  37
  38 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  39 #include "cpu/x86/bist.h"
  40
  41 #include "northbridge/amd/amdk8/setup_resource_map.c"
  42
  43 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  44
  45 static void hard_reset(void)
  46 {
  47         device_t dev;
  48
  49         /* Find the device */
  50         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
  51
  52         set_bios_reset();
  53
  54         /* enable cf9 */
  55         pci_write_config8(dev, 0x41, 0xf1);
  56         /* reset */
  57         outb(0x0e, 0x0cf9);
  58 }
  59
  60 static void soft_reset(void)
  61 {
  62         device_t dev;
  63
  64         /* Find the device */
  65         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
  66
  67         set_bios_reset();
  68         pci_write_config8(dev, 0x47, 1);
  69 }
  70
  71 static void memreset_setup(void)
  72 {
  73    if (is_cpu_pre_c0()) {
  74         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  75    }
  76    else {
  77         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  78    }
  79         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  80 }
  81
  82 static void memreset(int controllers, const struct mem_controller *ctrl)
  83 {
  84    if (is_cpu_pre_c0()) {
  85         udelay(800);
  86         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  87         udelay(90);
  88    }
  89 }
  90
  91 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  92 {
  93         /* nothing to do */
  94 }
  95
  96 static inline int spd_read_byte(unsigned device, unsigned address)
  97 {
  98         return smbus_read_byte(device, address);
  99 }
 100
 101
 102 #include "northbridge/amd/amdk8/raminit.c"
 103 #include "resourcemap.c"
 104 #include "northbridge/amd/amdk8/coherent_ht.c"
 105 #include "sdram/generic_sdram.c"
 106
 107 #include "cpu/amd/dualcore/dualcore.c"
 108
 109
 110 #include "cpu/amd/car/copy_and_run.c"
 111
 112 #include "cpu/amd/car/post_cache_as_ram.c"
 113
 114 #include "cpu/amd/model_fxx/init_cpus.c"
 115
 116
 117 #if USE_FALLBACK_IMAGE == 1
 118
 119 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 123 {
 124         unsigned last_boot_normal_x = last_boot_normal();
 125
 126         /* Is this a cpu only reset? or Is this a secondary cpu? */
 127         if ((cpu_init_detectedx) || (!boot_cpu())) {
 128                 if (last_boot_normal_x) {
 129                         goto normal_image;
 130                 } else {
 131                         goto fallback_image;
 132                 }
 133         }
 134
 135         /* Nothing special needs to be done to find bus 0 */
 136         /* Allow the HT devices to be found */
 137
 138         enumerate_ht_chain();
 139
 140         amd8111_enable_rom();
 141
 142         /* Is this a deliberate reset by the bios */
 143         if (bios_reset_detected() && last_boot_normal_x) {
 144                 goto normal_image;
 145         }
 146         /* This is the primary cpu how should I boot? */
 147         else if (do_normal_boot()) {
 148                 goto normal_image;
 149         }
 150         else {
 151                 goto fallback_image;
 152         }
 153  normal_image:
 154         __asm__ volatile ("jmp __normal_image"
 155                 : /* outputs */
 156                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 157                 );
 158
 159  fallback_image:
 160         ;
 161 }
 162 #endif
 163
 164 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 165
 166 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 167 {
 168
 169 #if USE_FALLBACK_IMAGE == 1
 170         failover_process(bist, cpu_init_detectedx);
 171 #endif
 172         real_main(bist, cpu_init_detectedx);
 173
 174 }
 175
 176 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 177 {
 178         static const uint16_t spd_addr [] = {
 179                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 180                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 181 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 182                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 183                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 184 #endif
 185         };
 186
 187         int needs_reset;
 188         unsigned cpu_reset = 0;
 189         unsigned bsp_apicid = 0;
 190
 191         struct mem_controller ctrl[8];
 192         unsigned nodes;
 193
 194         if (bist == 0) {
 195                 bsp_apicid = init_cpus(cpu_init_detectedx);
 196         }
 197
 198
 199         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 200         uart_init();
 201         console_init();
 202
 203         /* Halt if there was a built in self test failure */
 204         report_bist_failure(bist);
 205
 206         setup_s2881_resource_map();
 207
 208         needs_reset = setup_coherent_ht_domain();
 209
 210 #if CONFIG_LOGICAL_CPUS==1
 211         // It is said that we should start core1 after all core0 launched
 212         wait_all_core0_started();
 213         start_other_cores();
 214 #endif
 215
 216         wait_all_aps_started(bsp_apicid);
 217
 218         needs_reset |= ht_setup_chains_x();
 219
 220         if (needs_reset) {
 221                 print_info("ht reset -\r\n");
 222                 soft_reset();
 223         }
 224
 225         enable_smbus();
 226
 227         allow_all_aps_stop(bsp_apicid);
 228
 229         nodes = get_nodes();
 230         //It's the time to set ctrl now;
 231         fill_mem_ctrl(nodes, ctrl, spd_addr);
 232
 233         memreset_setup();
 234         sdram_initialize(nodes, ctrl);
 235
 236
 237         post_cache_as_ram(cpu_reset);
 238 }