src/mainboard/tyan/s2881/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void soft2_reset(void)
  47 {
  48         set_bios_reset();
  49         pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
  50 }
  51
  52 static void memreset_setup(void)
  53 {
  54    if (is_cpu_pre_c0()) {
  55         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  56    }
  57    else {
  58         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  59    }
  60         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65    if (is_cpu_pre_c0()) {
  66         udelay(800);
  67         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  68         udelay(90);
  69    }
  70 }
  71
  72 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  73 {
  74         /* Routing Table Node i
  75          *
  76          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  77          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  78          *
  79          * [ 0: 3] Request Route
  80          *     [0] Route to this node
  81          *     [1] Route to Link 0
  82          *     [2] Route to Link 1
  83          *     [3] Route to Link 2
  84          * [11: 8] Response Route
  85          *     [0] Route to this node
  86          *     [1] Route to Link 0
  87          *     [2] Route to Link 1
  88          *     [3] Route to Link 2
  89          * [19:16] Broadcast route
  90          *     [0] Route to this node
  91          *     [1] Route to Link 0
  92          *     [2] Route to Link 1
  93          *     [3] Route to Link 2
  94          */
  95
  96         uint32_t ret=0x00010101; /* default row entry */
  97         /* Link0 of CPU0 to Link0 of CPU1 */
  98         static const unsigned int rows_2p[2][2] = {
  99                 { 0x00030101, 0x00010202 },
 100                 { 0x00010202, 0x00030101 }
 101         };
 102
 103         if(maxnodes>2) {
 104                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 105                 maxnodes=2;
 106         }
 107
 108
 109         if (!(node>=maxnodes || row>=maxnodes)) {
 110                 ret=rows_2p[node][row];
 111         }
 112
 113         return ret;
 114 }
 115
 116 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 117 {
 118         /* nothing to do */
 119 }
 120
 121 static inline int spd_read_byte(unsigned device, unsigned address)
 122 {
 123         return smbus_read_byte(device, address);
 124 }
 125
 126 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 127 #include "northbridge/amd/amdk8/raminit.c"
 128 #include "northbridge/amd/amdk8/coherent_ht.c"
 129 #include "sdram/generic_sdram.c"
 130
 131  /* tyan does not want the default */
 132 #include "resourcemap.c"
 133
 134 #define FIRST_CPU  1
 135 #define SECOND_CPU 1
 136 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 137 static void main(unsigned long bist)
 138 {
 139         static const struct mem_controller cpu[] = {
 140 #if FIRST_CPU
 141                 {
 142                         .node_id = 0,
 143                         .f0 = PCI_DEV(0, 0x18, 0),
 144                         .f1 = PCI_DEV(0, 0x18, 1),
 145                         .f2 = PCI_DEV(0, 0x18, 2),
 146                         .f3 = PCI_DEV(0, 0x18, 3),
 147                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 148                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 149                 },
 150 #endif
 151 #if SECOND_CPU
 152                 {
 153                         .node_id = 1,
 154                         .f0 = PCI_DEV(0, 0x19, 0),
 155                         .f1 = PCI_DEV(0, 0x19, 1),
 156                         .f2 = PCI_DEV(0, 0x19, 2),
 157                         .f3 = PCI_DEV(0, 0x19, 3),
 158                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 159                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 160                 },
 161 #endif
 162         };
 163         int needs_reset;
 164         unsigned nodeid;
 165
 166         if (bist == 0) {
 167                 /* Skip this if there was a built in self test failure */
 168                 amd_early_mtrr_init();
 169                 enable_lapic();
 170                 init_timer();
 171
 172                 nodeid = lapicid() & 0xf;
 173
 174                 if (cpu_init_detected(nodeid)) {
 175                         asm volatile ("jmp __cpu_reset");
 176                 }
 177                 distinguish_cpu_resets(nodeid);
 178                 if (!boot_cpu()) {
 179                         stop_this_cpu();
 180                 }
 181         }
 182
 183         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 184         uart_init();
 185         console_init();
 186
 187         /* Halt if there was a built in self test failure */
 188 //      report_bist_failure(bist);
 189
 190         setup_s2881_resource_map();
 191         needs_reset = setup_coherent_ht_domain();
 192         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
 193         if (needs_reset) {
 194                 print_info("ht reset -\r\n");
 195                 soft_reset();
 196         }
 197
 198 #if 0
 199         print_pci_devices();
 200 #endif
 201         enable_smbus();
 202 #if 0
 203         dump_spd_registers(&cpu[0]);
 204 #endif
 205         memreset_setup();
 206         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 207
 208 #if 0
 209         dump_pci_devices();
 210 #endif
 211 #if 0
 212         dump_pci_device(PCI_DEV(0, 0x18, 1));
 213 #endif
 214
 215         /* Check all of memory */
 216 #if 0
 217         msr_t msr;
 218         msr = rdmsr(TOP_MEM2);
 219         print_debug("TOP_MEM2: ");
 220         print_debug_hex32(msr.hi);
 221         print_debug_hex32(msr.lo);
 222         print_debug("\r\n");
 223 #endif
 224 /*
 225 #if  0
 226         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 227 #else
 228 #if TOTAL_CPUS < 2
 229         // Check 16MB of memory @ 0
 230         ram_check(0x00000000, 0x01000000);
 231 #else
 232         // Check 16MB of memory @ 2GB
 233         ram_check(0x80000000, 0x81000000);
 234 #endif
 235 #endif
 236 */
 237 }