src/mainboard/tyan/s2881/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 static void hard_reset(void)
  31 {
  32         set_bios_reset();
  33
  34         /* enable cf9 */
  35         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  36         /* reset */
  37         outb(0x0e, 0x0cf9);
  38 }
  39
  40 static void soft_reset(void)
  41 {
  42         set_bios_reset();
  43         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  44 }
  45
  46 static void memreset_setup(void)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  50    }
  51    else {
  52         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  53    }
  54         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59    if (is_cpu_pre_c0()) {
  60         udelay(800);
  61         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  62         udelay(90);
  63    }
  64 }
  65
  66 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  67 {
  68         /* nothing to do */
  69 }
  70
  71 static inline int spd_read_byte(unsigned device, unsigned address)
  72 {
  73         return smbus_read_byte(device, address);
  74 }
  75
  76 //#include "northbridge/amd/amdk8/setup_resource_map.c"
  77 #define K8_4RANK_DIMM_SUPPORT 1
  78 #include "northbridge/amd/amdk8/raminit.c"
  79 #include "northbridge/amd/amdk8/coherent_ht.c"
  80 #include "sdram/generic_sdram.c"
  81
  82  /* tyan does not want the default */
  83 #include "resourcemap.c"
  84
  85 #if CONFIG_LOGICAL_CPUS==1
  86 #define SET_NB_CFG_54 1
  87 #include "cpu/amd/dualcore/dualcore.c"
  88 #endif
  89
  90 #define FIRST_CPU  1
  91 #define SECOND_CPU 1
  92 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  93 static void main(unsigned long bist)
  94 {
  95         static const struct mem_controller cpu[] = {
  96 #if FIRST_CPU
  97                 {
  98                         .node_id = 0,
  99                         .f0 = PCI_DEV(0, 0x18, 0),
 100                         .f1 = PCI_DEV(0, 0x18, 1),
 101                         .f2 = PCI_DEV(0, 0x18, 2),
 102                         .f3 = PCI_DEV(0, 0x18, 3),
 103                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 104                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 105                 },
 106 #endif
 107 #if SECOND_CPU
 108                 {
 109                         .node_id = 1,
 110                         .f0 = PCI_DEV(0, 0x19, 0),
 111                         .f1 = PCI_DEV(0, 0x19, 1),
 112                         .f2 = PCI_DEV(0, 0x19, 2),
 113                         .f3 = PCI_DEV(0, 0x19, 3),
 114                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 115                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 116                 },
 117 #endif
 118         };
 119         int needs_reset;
 120 #if CONFIG_LOGICAL_CPUS==1
 121         struct node_core_id id;
 122 #else
 123         unsigned nodeid;
 124 #endif
 125
 126         if (bist == 0) {
 127                 /* Skip this if there was a built in self test failure */
 128                 amd_early_mtrr_init();
 129
 130 #if CONFIG_LOGICAL_CPUS==1
 131                 set_apicid_cpuid_lo();
 132 #endif
 133
 134                 enable_lapic();
 135                 init_timer();
 136
 137 #if CONFIG_LOGICAL_CPUS==1
 138                 id = get_node_core_id_x();
 139                 if(id.coreid == 0) {
 140                         if (cpu_init_detected(id.nodeid)) {
 141                                 asm volatile ("jmp __cpu_reset");
 142                         }
 143                         distinguish_cpu_resets(id.nodeid);
 144                 }
 145 #else
 146                 nodeid = lapicid();
 147                 if (cpu_init_detected(nodeid)) {
 148                         asm volatile ("jmp __cpu_reset");
 149                 }
 150                 distinguish_cpu_resets(nodeid);
 151 #endif
 152
 153                 if (!boot_cpu()
 154 #if CONFIG_LOGICAL_CPUS==1
 155                         || (id.coreid != 0)
 156 #endif
 157                 ) {
 158                         stop_this_cpu();
 159                 }
 160         }
 161
 162         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 163         uart_init();
 164         console_init();
 165
 166         /* Halt if there was a built in self test failure */
 167 //        report_bist_failure(bist);
 168
 169         setup_s2881_resource_map();
 170         needs_reset = setup_coherent_ht_domain();
 171 #if CONFIG_LOGICAL_CPUS==1
 172         start_other_cores();
 173 #endif
 174         // automatically set that for you, but you might meet tight space
 175         needs_reset |= ht_setup_chains_x();
 176         if (needs_reset) {
 177                 print_info("ht reset -\r\n");
 178                 soft_reset();
 179         }
 180
 181         enable_smbus();
 182         memreset_setup();
 183         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 184
 185 }