1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses CONFIG_MAINBOARD_VENDOR
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
40 uses CONFIG_TTYS0_BAUD
41 uses CONFIG_TTYS0_BASE
43 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
44 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
45 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
47 uses CONFIG_HAVE_INIT_TIMER
50 uses CONFIG_CROSS_COMPILE
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
56 uses CONFIG_HW_MEM_HOLE_SIZEK
58 uses CONFIG_HT_CHAIN_UNITID_BASE
59 uses CONFIG_HT_CHAIN_END_UNITID_BASE
60 uses CONFIG_SB_HT_CHAIN_ON_BUS0
61 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
63 uses CONFIG_USE_DCACHE_RAM
64 uses CONFIG_DCACHE_RAM_BASE
65 uses CONFIG_DCACHE_RAM_SIZE
67 uses CONFIG_USE_PRINTK_IN_CAR
74 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
76 default CONFIG_ROM_SIZE=524288
79 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
81 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
84 ## Build code for the fallback boot
86 default CONFIG_HAVE_FALLBACK_BOOT=1
89 ## Build code to reset the motherboard from coreboot
91 default CONFIG_HAVE_HARD_RESET=1
94 ## Build code to export a programmable irq routing table
96 default CONFIG_HAVE_PIRQ_TABLE=1
97 default CONFIG_IRQ_SLOT_COUNT=9
100 ## Build code to export an x86 MP table
101 ## Useful for specifying IRQ routing values
103 default CONFIG_HAVE_MP_TABLE=1
106 ## Build code to export a CMOS option table
108 default CONFIG_HAVE_OPTION_TABLE=1
111 ## Move the default coreboot cmos range off of AMD RTC registers
113 default CONFIG_LB_CKS_RANGE_START=49
114 default CONFIG_LB_CKS_RANGE_END=122
115 default CONFIG_LB_CKS_LOC=123
118 ## Build code for SMP support
119 ## Only worry about 2 micro processors
122 default CONFIG_MAX_CPUS=4
123 default CONFIG_MAX_PHYSICAL_CPUS=2
124 default CONFIG_LOGICAL_CPUS=1
126 ##HT Unit ID offset, default is 1, the typical one
127 default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
129 ##real SB Unit ID, default is 0x20, mean dont touch it at last
130 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
132 #make the SB HT chain on bus 0, default is not (0)
133 default CONFIG_SB_HT_CHAIN_ON_BUS0=0
135 ##only offset for SB chain?, default is yes(1)
136 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
139 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
142 default CONFIG_CONSOLE_VGA=1
143 default CONFIG_PCI_ROM_RUN=1
147 ## enable CACHE_AS_RAM specifics
149 default CONFIG_USE_DCACHE_RAM=1
150 default CONFIG_DCACHE_RAM_BASE=0xcf000
151 default CONFIG_DCACHE_RAM_SIZE=0x1000
152 default CONFIG_USE_INIT=0
155 ## Build code to setup a generic IOAPIC
157 default CONFIG_IOAPIC=1
160 ## Clean up the motherboard id strings
162 default CONFIG_MAINBOARD_PART_NUMBER="s2881"
163 default CONFIG_MAINBOARD_VENDOR="Tyan"
164 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
165 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
168 ### coreboot layout values
171 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
172 default CONFIG_ROM_IMAGE_SIZE = 65536
175 ## Use a small 8K stack
177 default CONFIG_STACK_SIZE=0x2000
180 ## Use a small 16K heap
182 default CONFIG_HEAP_SIZE=0x4000
185 ## Only use the option table in a normal image
187 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
190 ## Coreboot C code runs at this location in RAM
192 default CONFIG_RAMBASE=0x00004000
195 ## Load the payload from the ROM
197 default CONFIG_ROM_PAYLOAD = 1
200 ### Defaults of options that you may want to override in the target config file
204 ## The default compiler
206 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
210 ## Disable the gdb stub by default
212 default CONFIG_GDB_STUB=0
214 default CONFIG_USE_PRINTK_IN_CAR=1
217 ## The Serial Console
220 # To Enable the Serial Console
221 default CONFIG_CONSOLE_SERIAL8250=1
223 ## Select the serial console baud rate
224 default CONFIG_TTYS0_BAUD=115200
225 #default CONFIG_TTYS0_BAUD=57600
226 #default CONFIG_TTYS0_BAUD=38400
227 #default CONFIG_TTYS0_BAUD=19200
228 #default CONFIG_TTYS0_BAUD=9600
229 #default CONFIG_TTYS0_BAUD=4800
230 #default CONFIG_TTYS0_BAUD=2400
231 #default CONFIG_TTYS0_BAUD=1200
233 # Select the serial console base port
234 default CONFIG_TTYS0_BASE=0x3f8
236 # Select the serial protocol
237 # This defaults to 8 data bits, 1 stop bit, and no parity
238 default CONFIG_TTYS0_LCS=0x3
241 ### Select the coreboot loglevel
243 ## EMERG 1 system is unusable
244 ## ALERT 2 action must be taken immediately
245 ## CRIT 3 critical conditions
246 ## ERR 4 error conditions
247 ## WARNING 5 warning conditions
248 ## NOTICE 6 normal but significant condition
249 ## INFO 7 informational
250 ## CONFIG_DEBUG 8 debug-level messages
251 ## SPEW 9 Way too many details
253 ## Request this level of debugging output
254 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
255 ## At a maximum only compile in this level of debugging
256 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
259 ## Select power on after power fail setting
260 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"