1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_XIP_ROM_SIZE
24 uses CONFIG_XIP_ROM_BASE
25 uses CONFIG_STACK_SIZE
27 uses CONFIG_USE_OPTION_TABLE
28 uses CONFIG_LB_CKS_RANGE_START
29 uses CONFIG_LB_CKS_RANGE_END
30 uses CONFIG_LB_CKS_LOC
31 uses CONFIG_MAINBOARD_PART_NUMBER
32 uses CONFIG_MAINBOARD_VENDOR
34 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
35 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
36 uses COREBOOT_EXTRA_VERSION
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
42 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
43 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
44 uses CONFIG_CONSOLE_SERIAL8250
45 uses CONFIG_HAVE_INIT_TIMER
48 uses CONFIG_CROSS_COMPILE
52 uses CONFIG_CONSOLE_VGA
53 uses CONFIG_PCI_ROM_RUN
54 uses CONFIG_HW_MEM_HOLE_SIZEK
56 uses CONFIG_HT_CHAIN_UNITID_BASE
57 uses CONFIG_HT_CHAIN_END_UNITID_BASE
58 uses CONFIG_SB_HT_CHAIN_ON_BUS0
59 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
61 uses CONFIG_USE_DCACHE_RAM
62 uses CONFIG_DCACHE_RAM_BASE
63 uses CONFIG_DCACHE_RAM_SIZE
65 uses CONFIG_USE_PRINTK_IN_CAR
72 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
74 default CONFIG_ROM_SIZE=524288
77 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
79 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
82 ## Build code for the fallback boot
84 default CONFIG_HAVE_FALLBACK_BOOT=1
87 ## Build code to reset the motherboard from coreboot
89 default CONFIG_HAVE_HARD_RESET=1
92 ## Build code to export a programmable irq routing table
94 default CONFIG_HAVE_PIRQ_TABLE=1
95 default CONFIG_IRQ_SLOT_COUNT=9
98 ## Build code to export an x86 MP table
99 ## Useful for specifying IRQ routing values
101 default CONFIG_HAVE_MP_TABLE=1
104 ## Build code to export a CMOS option table
106 default CONFIG_HAVE_OPTION_TABLE=1
109 ## Move the default coreboot cmos range off of AMD RTC registers
111 default CONFIG_LB_CKS_RANGE_START=49
112 default CONFIG_LB_CKS_RANGE_END=122
113 default CONFIG_LB_CKS_LOC=123
116 ## Build code for SMP support
117 ## Only worry about 2 micro processors
120 default CONFIG_MAX_CPUS=4
121 default CONFIG_MAX_PHYSICAL_CPUS=2
122 default CONFIG_LOGICAL_CPUS=1
124 ##HT Unit ID offset, default is 1, the typical one
125 default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
127 ##real SB Unit ID, default is 0x20, mean dont touch it at last
128 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
130 #make the SB HT chain on bus 0, default is not (0)
131 default CONFIG_SB_HT_CHAIN_ON_BUS0=0
133 ##only offset for SB chain?, default is yes(1)
134 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
137 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
140 default CONFIG_CONSOLE_VGA=1
141 default CONFIG_PCI_ROM_RUN=1
145 ## enable CACHE_AS_RAM specifics
147 default CONFIG_USE_DCACHE_RAM=1
148 default CONFIG_DCACHE_RAM_BASE=0xcf000
149 default CONFIG_DCACHE_RAM_SIZE=0x1000
150 default CONFIG_USE_INIT=0
153 ## Build code to setup a generic IOAPIC
155 default CONFIG_IOAPIC=1
158 ## Clean up the motherboard id strings
160 default CONFIG_MAINBOARD_PART_NUMBER="s2881"
161 default CONFIG_MAINBOARD_VENDOR="Tyan"
162 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
163 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
166 ### coreboot layout values
169 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
170 default CONFIG_ROM_IMAGE_SIZE = 65536
173 ## Use a small 8K stack
175 default CONFIG_STACK_SIZE=0x2000
178 ## Use a small 16K heap
180 default CONFIG_HEAP_SIZE=0x4000
183 ## Only use the option table in a normal image
185 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
188 ## Coreboot C code runs at this location in RAM
190 default CONFIG_RAMBASE=0x00004000
193 ## Load the payload from the ROM
195 default CONFIG_ROM_PAYLOAD = 1
198 ### Defaults of options that you may want to override in the target config file
202 ## The default compiler
204 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
208 ## Disable the gdb stub by default
210 default CONFIG_GDB_STUB=0
212 default CONFIG_USE_PRINTK_IN_CAR=1
215 ## The Serial Console
218 # To Enable the Serial Console
219 default CONFIG_CONSOLE_SERIAL8250=1
221 ## Select the serial console baud rate
222 default CONFIG_TTYS0_BAUD=115200
223 #default CONFIG_TTYS0_BAUD=57600
224 #default CONFIG_TTYS0_BAUD=38400
225 #default CONFIG_TTYS0_BAUD=19200
226 #default CONFIG_TTYS0_BAUD=9600
227 #default CONFIG_TTYS0_BAUD=4800
228 #default CONFIG_TTYS0_BAUD=2400
229 #default CONFIG_TTYS0_BAUD=1200
231 # Select the serial console base port
232 default CONFIG_TTYS0_BASE=0x3f8
234 # Select the serial protocol
235 # This defaults to 8 data bits, 1 stop bit, and no parity
236 default CONFIG_TTYS0_LCS=0x3
239 ### Select the coreboot loglevel
241 ## EMERG 1 system is unusable
242 ## ALERT 2 action must be taken immediately
243 ## CRIT 3 critical conditions
244 ## ERR 4 error conditions
245 ## WARNING 5 warning conditions
246 ## NOTICE 6 normal but significant condition
247 ## INFO 7 informational
248 ## CONFIG_DEBUG 8 debug-level messages
249 ## SPEW 9 Way too many details
251 ## Request this level of debugging output
252 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
253 ## At a maximum only compile in this level of debugging
254 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
257 ## Select power on after power fail setting
258 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"