src/mainboard/tyan/s2881/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 #
  10 #
  11 ###
  12 ### Set all of the defaults for an x86 architecture
  13 ###
  14 #
  15 #
  16 ###
  17 ### Build the objects we have code for in this directory.
  18 ###
  19 ##object mainboard.o
  20 config chip.h
  21 register "fixup_scsi" = "1"
  22 register "fixup_vga" = "1"
  23
  24
  25 ##
  26 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  27 ##
  28 default LB_CKS_RANGE_START=49
  29 default LB_CKS_RANGE_END=122
  30 default LB_CKS_LOC=123
  31
  32
  33 driver mainboard.o
  34 #driver adaptec_scsi.o
  35 #driver si_sata.o
  36 #driver intel_nic.o
  37 #driver broadcom_nic.o
  38 object reset.o
  39 if HAVE_MP_TABLE object mptable.o end
  40 if HAVE_PIRQ_TABLE object irq_tables.o end
  41 #
  42 arch i386 end
  43 #cpu k8 end
  44 #
  45 ###
  46 ### Build our 16 bit and 32 bit linuxBIOS entry code
  47 ###
  48 mainboardinit cpu/i386/entry16.inc
  49 mainboardinit cpu/i386/entry32.inc
  50 mainboardinit cpu/i386/bist32.inc
  51 ldscript /cpu/i386/entry16.lds
  52 ldscript /cpu/i386/entry32.lds
  53 #
  54 ###
  55 ### Build our reset vector (This is where linuxBIOS is entered)
  56 ###
  57 if USE_FALLBACK_IMAGE
  58         mainboardinit cpu/i386/reset16.inc
  59         ldscript /cpu/i386/reset16.lds
  60 else
  61         mainboardinit cpu/i386/reset32.inc
  62         ldscript /cpu/i386/reset32.lds
  63 end
  64 #
  65 #### Should this be in the northbridge code?
  66 mainboardinit arch/i386/lib/cpu_reset.inc
  67 #
  68 ###
  69 ### Include an id string (For safe flashing)
  70 ###
  71 mainboardinit arch/i386/lib/id.inc
  72 ldscript /arch/i386/lib/id.lds
  73 #
  74 ####
  75 #### This is the early phase of linuxBIOS startup
  76 #### Things are delicate and we test to see if we should
  77 #### failover to another image.
  78 ####
  79 #option MAX_REBOOT_CNT=2
  80 if USE_FALLBACK_IMAGE
  81   ldscript /arch/i386/lib/failover.lds
  82 end
  83 #
  84 ###
  85 ### Setup our mtrrs
  86 ###
  87 mainboardinit cpu/k8/earlymtrr.inc
  88 ###
  89 ### Only the bootstrap cpu makes it here.
  90 ### Failover if we need to
  91 ###
  92 #
  93 if USE_FALLBACK_IMAGE
  94   mainboardinit ./failover.inc
  95 end
  96
  97 #
  98 #
  99 ###
 100 ### Setup the serial port
 101 ###
 102 mainboardinit pc80/serial.inc
 103 mainboardinit arch/i386/lib/console.inc
 104 mainboardinit cpu/i386/bist32_fail.inc
 105 #
 106 ####
 107 #### O.k. We aren't just an intermediary anymore!
 108 ####
 109 #
 110 ###
 111 ### Romcc output
 112 ###
 113 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
 114 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
 115 #mainboardinit .failover.inc
 116
 117 makerule ./failover.E
 118         depends "$(MAINBOARD)/failover.c"
 119         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 120 end
 121
 122 makerule ./failover.inc
 123         depends "./romcc ./failover.E"
 124         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 125
 126 makerule ./auto.E
 127         depends "$(MAINBOARD)/auto.c option_table.h"
 128         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 129 end
 130 makerule ./auto.inc
 131         depends "./romcc ./auto.E"
 132         action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 133 #       action  "./romcc -mcpu=k8  -O ./auto.E > auto.inc"
 134 end
 135 mainboardinit cpu/k8/enable_mmx_sse.inc
 136 mainboardinit ./auto.inc
 137 mainboardinit cpu/k8/disable_mmx_sse.inc
 138 #
 139 ###
 140 ### Include the secondary Configuration files
 141 ###
 142 northbridge amd/amdk8 "mc0"
 143         pci 0:18.0
 144         pci 0:18.0
 145         pci 0:18.0
 146         pci 0:18.1
 147         pci 0:18.2
 148         pci 0:18.3
 149         southbridge amd/amd8131 "amd8131" link 2
 150                 pci 0:0.0
 151                 pci 0:0.1
 152                 pci 0:1.0
 153                 pci 0:1.1
 154         end
 155         southbridge amd/amd8111 "amd8111" link 2
 156                 pci 0:0.0
 157                 pci 0:1.0 on
 158                 pci 0:1.1 on
 159                 pci 0:1.2 on
 160                 pci 0:1.3 on
 161                 pci 0:1.5 off
 162                 pci 0:1.6 off
 163                 pci 1:0.0 on
 164                 pci 1:0.1 on
 165                 pci 1:0.2 on
 166                 pci 1:1.0 off
 167                 superio winbond/w83627hf link 1
 168                         pnp 2e.0 off #  Floppy
 169                                  io 0x60 = 0x3f0
 170                                 irq 0x70 = 6
 171                                 drq 0x74 = 2
 172                         pnp 2e.1 off #  Parallel Port
 173                                  io 0x60 = 0x378
 174                                 irq 0x70 = 7
 175                         pnp 2e.2 on #  Com1
 176                                  io 0x60 = 0x3f8
 177                                 irq 0x70 = 4
 178                         pnp 2e.3 off #  Com2
 179                                  io 0x60 = 0x2f8
 180                                 irq 0x70 = 3
 181                         pnp 2e.5 on #  Keyboard
 182                                  io 0x60 = 0x60
 183                                  io 0x62 = 0x64
 184                                 irq 0x70 = 1
 185                         pnp 2e.6 off #  CIR
 186                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 187                         pnp 2e.8 off #  GPIO2
 188                         pnp 2e.9 off #  GPIO3
 189                         pnp 2e.a off #  ACPI
 190                         pnp 2e.b off #  HW Monitor
 191                 end
 192         end
 193 end
 194
 195 northbridge amd/amdk8 "mc1"
 196         pci 0:19.0
 197         pci 0:19.0
 198         pci 0:19.0
 199         pci 0:19.1
 200         pci 0:19.2
 201         pci 0:19.3
 202 end
 203
 204
 205 dir /pc80
 206 #dir /bioscall
 207 cpu k8 "cpu0"
 208   register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 209 end
 210
 211 cpu k8 "cpu1"
 212 end