2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/failover.c ./romcc"
52 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
55 makerule ./failover.inc
56 depends "$(MAINBOARD)/failover.c ./romcc"
57 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
61 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
62 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
65 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
66 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
70 ## Build our 16 bit and 32 bit linuxBIOS entry code
72 mainboardinit cpu/x86/16bit/entry16.inc
73 mainboardinit cpu/x86/32bit/entry32.inc
74 ldscript /cpu/x86/16bit/entry16.lds
75 ldscript /cpu/x86/32bit/entry32.lds
78 ## Build our reset vector (This is where linuxBIOS is entered)
81 mainboardinit cpu/x86/16bit/reset16.inc
82 ldscript /cpu/x86/16bit/reset16.lds
84 mainboardinit cpu/x86/32bit/reset32.inc
85 ldscript /cpu/x86/32bit/reset32.lds
88 ### Should this be in the northbridge code?
89 mainboardinit arch/i386/lib/cpu_reset.inc
92 ## Include an id string (For safe flashing)
94 mainboardinit arch/i386/lib/id.inc
95 ldscript /arch/i386/lib/id.lds
98 ### This is the early phase of linuxBIOS startup
99 ### Things are delicate and we test to see if we should
100 ### failover to another image.
102 if USE_FALLBACK_IMAGE
103 ldscript /arch/i386/lib/failover.lds
104 mainboardinit ./failover.inc
108 ### O.k. We aren't just an intermediary anymore!
114 mainboardinit cpu/x86/fpu/enable_fpu.inc
115 mainboardinit cpu/x86/mmx/enable_mmx.inc
116 mainboardinit cpu/x86/sse/enable_sse.inc
117 mainboardinit ./auto.inc
118 mainboardinit cpu/x86/sse/disable_sse.inc
119 mainboardinit cpu/x86/mmx/disable_mmx.inc
122 ## Include the secondary Configuration files
127 # sample config for tyan/s2881
128 chip northbridge/amd/amdk8
129 device pci_domain 0 on
130 device pci 18.0 on end # LDT0
131 device pci 18.0 on end # LDT1
132 device pci 18.0 on # northbridge
133 # devices on link 2, link 2 == LDT 2
134 chip southbridge/amd/amd8131
135 # the on/off keyword is mandatory
136 device pci 0.0 on end
137 device pci 0.1 on end
138 device pci 1.0 on end
139 device pci 1.1 on end
141 chip southbridge/amd/amd8111
142 # this "device pci 0.0" is the parent the next one
145 device pci 0.0 on end
146 device pci 0.1 on end
147 device pci 0.2 off end
148 device pci 1.0 off end
151 chip superio/winbond/w83627hf
152 device pnp 2e.0 on # Floppy
157 device pnp 2e.1 off # Parallel Port
161 device pnp 2e.2 on # Com1
165 device pnp 2e.3 off # Com2
169 device pnp 2e.5 on # Keyboard
175 device pnp 2e.6 off # CIR
178 device pnp 2e.7 off # GAME_MIDI_GIPO1
183 device pnp 2e.8 off end # GPIO2
184 device pnp 2e.9 off end # GPIO3
185 device pnp 2e.a off end # ACPI
186 device pnp 2e.b on # HW Monitor
192 device pci 1.1 on end
193 device pci 1.2 on end
194 device pci 1.3 on end
195 device pci 1.5 off end
196 device pci 1.6 off end
198 end # device pci 18.0
200 device pci 18.1 on end
201 device pci 18.2 on end
202 device pci 18.3 on end
204 chip northbridge/amd/amdk8
205 device pci 19.0 on end
206 device pci 19.0 on end
207 device pci 19.0 on end
208 device pci 19.1 on end
209 device pci 19.2 on end
210 device pci 19.3 on end
213 device apic_cluster 0 on
214 chip cpu/amd/socket_940
217 chip cpu/amd/socket_940