2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/failover.c ./romcc"
52 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
55 makerule ./failover.inc
56 depends "$(MAINBOARD)/failover.c ./romcc"
57 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
61 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
62 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
65 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
66 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
70 ## Build our 16 bit and 32 bit linuxBIOS entry code
72 mainboardinit cpu/x86/16bit/entry16.inc
73 mainboardinit cpu/x86/32bit/entry32.inc
74 ldscript /cpu/x86/16bit/entry16.lds
75 ldscript /cpu/x86/32bit/entry32.lds
78 ## Build our reset vector (This is where linuxBIOS is entered)
81 mainboardinit cpu/x86/16bit/reset16.inc
82 ldscript /cpu/x86/16bit/reset16.lds
84 mainboardinit cpu/x86/32bit/reset32.inc
85 ldscript /cpu/x86/32bit/reset32.lds
88 ### Should this be in the northbridge code?
89 mainboardinit arch/i386/lib/cpu_reset.inc
92 ## Include an id string (For safe flashing)
94 mainboardinit arch/i386/lib/id.inc
95 ldscript /arch/i386/lib/id.lds
98 ### This is the early phase of linuxBIOS startup
99 ### Things are delicate and we test to see if we should
100 ### failover to another image.
102 if USE_FALLBACK_IMAGE
103 ldscript /arch/i386/lib/failover.lds
104 mainboardinit ./failover.inc
108 ### O.k. We aren't just an intermediary anymore!
114 mainboardinit cpu/x86/fpu/enable_fpu.inc
115 mainboardinit cpu/x86/mmx/enable_mmx.inc
116 mainboardinit cpu/x86/sse/enable_sse.inc
117 mainboardinit ./auto.inc
118 mainboardinit cpu/x86/sse/disable_sse.inc
119 mainboardinit cpu/x86/mmx/disable_mmx.inc
122 ## Include the secondary Configuration files
128 # sample config for tyan/s2881
129 chip northbridge/amd/amdk8/root_complex
130 device apic_cluster 0 on
131 chip cpu/amd/socket_940
135 device pci_domain 0 on
136 chip northbridge/amd/amdk8
137 device pci 18.0 on end # LDT0
138 device pci 18.0 on end # LDT1
139 device pci 18.0 on # northbridge
140 # devices on link 2, link 2 == LDT 2
141 chip southbridge/amd/amd8131
142 # the on/off keyword is mandatory
144 chip drivers/pci/onboard
145 device pci 9.0 on end # Broadcom 5704
146 device pci 9.1 on end
148 chip drivers/pci/onboard
149 device pci a.0 on end # Adaptic
150 device pci a.1 on end
153 device pci 0.1 on end
154 device pci 1.0 on end
155 device pci 1.1 on end
157 chip southbridge/amd/amd8111
158 # this "device pci 0.0" is the parent the next one
161 device pci 0.0 on end
162 device pci 0.1 on end
163 device pci 0.2 off end
164 device pci 1.0 off end
165 chip drivers/pci/onboard
166 device pci 5.0 on end # SiI
168 chip drivers/pci/onboard
169 device pci 6.0 on end
170 register "rom_address" = "0xfff80000"
174 chip superio/winbond/w83627hf
175 device pnp 2e.0 on # Floppy
180 device pnp 2e.1 off # Parallel Port
184 device pnp 2e.2 on # Com1
188 device pnp 2e.3 off # Com2
192 device pnp 2e.5 on # Keyboard
198 device pnp 2e.6 off # CIR
201 device pnp 2e.7 off # GAME_MIDI_GIPO1
206 device pnp 2e.8 off end # GPIO2
207 device pnp 2e.9 off end # GPIO3
208 device pnp 2e.a off end # ACPI
209 device pnp 2e.b on # HW Monitor
215 device pci 1.1 on end
216 device pci 1.2 on end
218 chip drivers/generic/generic #dimm 0-0-0
221 chip drivers/generic/generic #dimm 0-0-1
224 chip drivers/generic/generic #dimm 0-1-0
227 chip drivers/generic/generic #dimm 0-1-1
230 chip drivers/generic/generic #dimm 1-0-0
233 chip drivers/generic/generic #dimm 1-0-1
236 chip drivers/generic/generic #dimm 1-1-0
239 chip drivers/generic/generic #dimm 1-1-1
242 chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3
245 chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN
248 chip drivers/generic/generic # Winbond HWM 0x92
251 chip drivers/generic/generic # Winbond HWM 0x94
255 device pci 1.5 off end
256 device pci 1.6 off end
257 register "ide0_enable" = "1"
258 register "ide1_enable" = "1"
260 end # device pci 18.0
262 device pci 18.1 on end
263 device pci 18.2 on end
264 device pci 18.3 on end