3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
9 #include <pc80/mc146818rtc.h>
10 #include <console/console.h>
14 #include <cpu/amd/model_fxx_rev.h>
15 #include "northbridge/amd/amdk8/incoherent_ht.c"
16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
17 #include "northbridge/amd/amdk8/raminit.h"
18 #include "cpu/amd/model_fxx/apic_timer.c"
19 #include "lib/delay.c"
21 #include "cpu/x86/lapic/boot_cpu.c"
22 #include "northbridge/amd/amdk8/reset_test.c"
23 #include "northbridge/amd/amdk8/debug.c"
24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
26 #include "cpu/x86/mtrr/earlymtrr.c"
27 #include "cpu/x86/bist.h"
29 #include "northbridge/amd/amdk8/setup_resource_map.c"
31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
35 static void memreset_setup(void)
37 if (is_cpu_pre_c0()) {
38 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
41 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
43 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
46 static void memreset(int controllers, const struct mem_controller *ctrl)
48 if (is_cpu_pre_c0()) {
50 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
60 static inline int spd_read_byte(unsigned device, unsigned address)
62 return smbus_read_byte(device, address);
66 #include "northbridge/amd/amdk8/raminit.c"
67 #include "northbridge/amd/amdk8/resourcemap.c"
68 #include "northbridge/amd/amdk8/coherent_ht.c"
69 #include "lib/generic_sdram.c"
71 #include "cpu/amd/dualcore/dualcore.c"
75 #include "cpu/amd/car/post_cache_as_ram.c"
77 #include "cpu/amd/model_fxx/init_cpus.c"
79 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
80 #include "northbridge/amd/amdk8/early_ht.c"
82 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
84 static const struct mem_controller cpu[] = {
87 .f0 = PCI_DEV(0, 0x18, 0),
88 .f1 = PCI_DEV(0, 0x18, 1),
89 .f2 = PCI_DEV(0, 0x18, 2),
90 .f3 = PCI_DEV(0, 0x18, 3),
91 .channel0 = { DIMM0, DIMM2, 0, 0 },
92 .channel1 = { DIMM1, DIMM3, 0, 0 },
94 #if CONFIG_MAX_PHYSICAL_CPUS > 1
97 .f0 = PCI_DEV(0, 0x19, 0),
98 .f1 = PCI_DEV(0, 0x19, 1),
99 .f2 = PCI_DEV(0, 0x19, 2),
100 .f3 = PCI_DEV(0, 0x19, 3),
101 .channel0 = { DIMM4, DIMM6, 0, 0 },
102 .channel1 = { DIMM5, DIMM7, 0, 0 },
109 if (!cpu_init_detectedx && boot_cpu()) {
110 /* Nothing special needs to be done to find bus 0 */
111 /* Allow the HT devices to be found */
113 enumerate_ht_chain();
115 amd8111_enable_rom();
119 init_cpus(cpu_init_detectedx);
123 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
127 /* Halt if there was a built in self test failure */
128 report_bist_failure(bist);
130 setup_default_resource_map();
132 needs_reset = setup_coherent_ht_domain();
134 #if CONFIG_LOGICAL_CPUS==1
135 // It is said that we should start core1 after all core0 launched
138 // automatically set that for you, but you might meet tight space
139 needs_reset |= ht_setup_chains_x();
142 print_info("ht reset -\n");
149 sdram_initialize(ARRAY_SIZE(cpu), cpu);