1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #if CONFIG_LOGICAL_CPUS==1
7 #include <cpu/amd/dualcore.h>
10 void *smp_write_config_table(void *v)
12 static const char sig[4] = "PCMP";
13 static const char oem[8] = "TYAN ";
14 static const char productid[12] = "S2880 ";
15 struct mp_config_table *mc;
17 unsigned char bus_num;
18 unsigned char bus_isa;
19 unsigned char bus_8131_1;
20 unsigned char bus_8131_2;
21 unsigned char bus_8111_1;
24 unsigned apicid_8131_1;
25 unsigned apicid_8131_2;
27 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
28 memset(mc, 0, sizeof(*mc));
30 memcpy(mc->mpc_signature, sig, sizeof(sig));
31 mc->mpc_length = sizeof(*mc); /* initially just the header */
33 mc->mpc_checksum = 0; /* not yet computed */
34 memcpy(mc->mpc_oem, oem, sizeof(oem));
35 memcpy(mc->mpc_productid, productid, sizeof(productid));
38 mc->mpc_entry_count = 0; /* No entries yet... */
39 mc->mpc_lapic = LAPIC_ADDR;
44 smp_write_processors(mc);
50 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
52 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
53 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
57 printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
63 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
65 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
69 printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
74 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
76 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
80 printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
87 /* define bus and isa numbers */
88 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
89 smp_write_bus(mc, bus_num, "PCI ");
91 smp_write_bus(mc, bus_isa, "ISA ");
94 /*I/O APICs: APIC ID Version State Address*/
95 #if CONFIG_LOGICAL_CPUS==1
96 apicid_base = get_apicid_base(3);
98 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
100 apicid_8111 = apicid_base+0;
101 apicid_8131_1 = apicid_base+1;
102 apicid_8131_2 = apicid_base+2;
103 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
107 struct resource *res;
108 dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
110 res = find_resource(dev, PCI_BASE_ADDRESS_0);
112 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
115 dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
117 res = find_resource(dev, PCI_BASE_ADDRESS_0);
119 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
125 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
126 */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3);
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6);
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8);
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd);
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
146 //On Board ATI Display Adapter
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
155 //On Board Promise Serial ATA
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0);
161 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);//
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);//
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);//
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);//
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, apicid_8131_1, 0x1);//
170 //On Board NIC and LSI scsi
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x0);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x1);
176 //Slot 1 PCI-X 133/100/66
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
182 //Slot 2 PCI-X 133/100/66
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x1);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x2);
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, apicid_8131_2, 0x3);//
186 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);//
188 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
189 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
190 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
191 /* There is no extension information... */
193 /* Compute the checksums */
194 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
195 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
196 printk_debug("Wrote the mp table end at: %p - %p\n",
197 mc, smp_next_mpe_entry(mc));
198 return smp_next_mpe_entry(mc);
201 unsigned long write_smp_table(unsigned long addr)
204 v = smp_write_floating_table(addr);
205 return (unsigned long)smp_write_config_table(v);