src/mainboard/tyan/s2880/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #if CONFIG_USE_INIT == 0
  25 #include "lib/memcpy.c"
  26 #endif
  27
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30 #include "northbridge/amd/amdk8/debug.c"
  31 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  32
  33 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  34 #include "cpu/x86/bist.h"
  35
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  41
  42 static void memreset_setup(void)
  43 {
  44    if (is_cpu_pre_c0()) {
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  46    }
  47    else {
  48         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  49    }
  50         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  51 }
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55    if (is_cpu_pre_c0()) {
  56         udelay(800);
  57         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  58         udelay(90);
  59    }
  60 }
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66
  67 static inline int spd_read_byte(unsigned device, unsigned address)
  68 {
  69         return smbus_read_byte(device, address);
  70 }
  71
  72 #define K8_4RANK_DIMM_SUPPORT 1
  73
  74 #include "northbridge/amd/amdk8/raminit.c"
  75 #include "northbridge/amd/amdk8/resourcemap.c"
  76 #include "northbridge/amd/amdk8/coherent_ht.c"
  77 #include "sdram/generic_sdram.c"
  78
  79 #if CONFIG_LOGICAL_CPUS==1
  80 #define SET_NB_CFG_54 1
  81 #endif
  82 #include "cpu/amd/dualcore/dualcore.c"
  83
  84 #include "cpu/amd/car/copy_and_run.c"
  85
  86 #include "cpu/amd/car/post_cache_as_ram.c"
  87
  88 #include "cpu/amd/model_fxx/init_cpus.c"
  89
  90
  91 #if USE_FALLBACK_IMAGE == 1
  92
  93 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  94 #include "northbridge/amd/amdk8/early_ht.c"
  95
  96 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98         unsigned last_boot_normal_x = last_boot_normal();
  99
 100         /* Is this a cpu only reset? or Is this a secondary cpu? */
 101         if ((cpu_init_detectedx) || (!boot_cpu())) {
 102                 if (last_boot_normal_x) {
 103                         goto normal_image;
 104                 } else {
 105                         goto fallback_image;
 106                 }
 107         }
 108
 109         /* Nothing special needs to be done to find bus 0 */
 110         /* Allow the HT devices to be found */
 111
 112         enumerate_ht_chain();
 113
 114         amd8111_enable_rom();
 115
 116         /* Is this a deliberate reset by the bios */
 117         if (bios_reset_detected() && last_boot_normal_x) {
 118                 goto normal_image;
 119         }
 120         /* This is the primary cpu how should I boot? */
 121         else if (do_normal_boot()) {
 122                 goto normal_image;
 123         }
 124         else {
 125                 goto fallback_image;
 126         }
 127  normal_image:
 128         __asm__ volatile ("jmp __normal_image"
 129                 : /* outputs */
 130                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 131                 );
 132
 133  fallback_image:
 134         ;
 135 }
 136 #endif
 137
 138 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 139
 140 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 141 {
 142
 143 #if USE_FALLBACK_IMAGE == 1
 144         failover_process(bist, cpu_init_detectedx);
 145 #endif
 146         real_main(bist, cpu_init_detectedx);
 147
 148 }
 149
 150 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 151 {
 152         static const struct mem_controller cpu[] = {
 153                 {
 154                         .node_id = 0,
 155                         .f0 = PCI_DEV(0, 0x18, 0),
 156                         .f1 = PCI_DEV(0, 0x18, 1),
 157                         .f2 = PCI_DEV(0, 0x18, 2),
 158                         .f3 = PCI_DEV(0, 0x18, 3),
 159                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 160                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 161                 },
 162 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 163                 {
 164                         .node_id = 1,
 165                         .f0 = PCI_DEV(0, 0x19, 0),
 166                         .f1 = PCI_DEV(0, 0x19, 1),
 167                         .f2 = PCI_DEV(0, 0x19, 2),
 168                         .f3 = PCI_DEV(0, 0x19, 3),
 169                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 170                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 171                 },
 172 #endif
 173         };
 174
 175         int needs_reset;
 176
 177         if (bist == 0) {
 178                 init_cpus(cpu_init_detectedx);
 179         }
 180
 181
 182         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 183         uart_init();
 184         console_init();
 185
 186         /* Halt if there was a built in self test failure */
 187         report_bist_failure(bist);
 188
 189         setup_default_resource_map();
 190
 191         needs_reset = setup_coherent_ht_domain();
 192
 193 #if CONFIG_LOGICAL_CPUS==1
 194         // It is said that we should start core1 after all core0 launched
 195         start_other_cores();
 196 #endif
 197         // automatically set that for you, but you might meet tight space
 198         needs_reset |= ht_setup_chains_x();
 199
 200         if (needs_reset) {
 201                 print_info("ht reset -\r\n");
 202                 soft_reset();
 203         }
 204
 205         enable_smbus();
 206
 207         memreset_setup();
 208         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 209
 210         post_cache_as_ram();
 211 }