src/mainboard/tyan/s2880/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <cpu/p6/apic.h>
   5 #include <arch/io.h>
   6 #include <arch/romcc_io.h>
   7 #include "pc80/serial.c"
   8 #include "arch/i386/lib/console.c"
   9 #include "ram/ramtest.c"
  10 #include "northbridge/amd/amdk8/early_ht.c"
  11 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  12 #include "northbridge/amd/amdk8/raminit.h"
  13 #include "cpu/k8/apic_timer.c"
  14 #include "lib/delay.c"
  15 #include "cpu/p6/boot_cpu.c"
  16 #include "northbridge/amd/amdk8/reset_test.c"
  17 #include "debug.c"
  18 #include "northbridge/amd/amdk8/cpu_rev.c"
  19
  20
  21 #define REV_B_RESET 0
  22 static void memreset_setup(void)
  23 {
  24 #if REV_B_RESET==1
  25         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  26 #else
  27         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  28 #endif
  29         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  30 }
  31
  32 static void memreset(int controllers, const struct mem_controller *ctrl)
  33 {
  34         udelay(800);
  35 #if REV_B_RESET==1
  36         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  37 #endif
  38         udelay(90);
  39 }
  40
  41 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  42 {
  43         /* Routing Table Node i
  44          *
  45          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  46          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  47          *
  48          * [ 0: 3] Request Route
  49          *     [0] Route to this node
  50          *     [1] Route to Link 0
  51          *     [2] Route to Link 1
  52          *     [3] Route to Link 2
  53          * [11: 8] Response Route
  54          *     [0] Route to this node
  55          *     [1] Route to Link 0
  56          *     [2] Route to Link 1
  57          *     [3] Route to Link 2
  58          * [19:16] Broadcast route
  59          *     [0] Route to this node
  60          *     [1] Route to Link 0
  61          *     [2] Route to Link 1
  62          *     [3] Route to Link 2
  63          */
  64
  65         uint32_t ret=0x00010101; /* default row entry */
  66
  67         static const unsigned int rows_2p[2][2] = {
  68                 { 0x00050101, 0x00010404 },
  69                 { 0x00010404, 0x00050101 }
  70         };
  71
  72         if(maxnodes>2) {
  73                 print_debug("this mainboard is only designed for 2 cpus\r\n");
  74                 maxnodes=2;
  75         }
  76
  77
  78         if (!(node>=maxnodes || row>=maxnodes)) {
  79                 ret=rows_2p[node][row];
  80         }
  81
  82         return ret;
  83 }
  84
  85 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  86 {
  87         /* nothing to do */
  88 }
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92         return smbus_read_byte(device, address);
  93 }
  94
  95 /* include mainboard specific ht code */
  96 #include "hypertransport.c"
  97
  98 //#include "northbridge/amd/amdk8/cpu_ldtstop.c"
  99 //#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
 100
 101 #include "northbridge/amd/amdk8/raminit.c"
 102 #include "northbridge/amd/amdk8/coherent_ht.c"
 103 #include "sdram/generic_sdram.c"
 104
 105 static void enable_lapic(void)
 106 {
 107         msr_t msr;
 108         msr = rdmsr(0x1b);
 109         msr.hi &= 0xffffff00;
 110         msr.lo &= 0x000007ff;
 111         msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
 112         wrmsr(0x1b, msr);
 113 }
 114
 115 static void stop_this_cpu(void)
 116 {
 117         unsigned apicid;
 118         apicid = apic_read(APIC_ID) >> 24;
 119
 120         /* Send an APIC INIT to myself */
 121         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 122         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
 123         /* Wait for the ipi send to finish */
 124         apic_wait_icr_idle();
 125
 126         /* Deassert the APIC INIT */
 127         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 128         apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
 129         /* Wait for the ipi send to finish */
 130         apic_wait_icr_idle();
 131
 132         /* If I haven't halted spin forever */
 133         for(;;) {
 134                 hlt();
 135         }
 136 }
 137 #define FIRST_CPU  1
 138 #define SECOND_CPU 1
 139 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 140 static void main(void)
 141 {
 142         static const struct mem_controller cpu[] = {
 143 #if FIRST_CPU
 144                 {
 145                         .node_id = 0,
 146                         .f0 = PCI_DEV(0, 0x18, 0),
 147                         .f1 = PCI_DEV(0, 0x18, 1),
 148                         .f2 = PCI_DEV(0, 0x18, 2),
 149                         .f3 = PCI_DEV(0, 0x18, 3),
 150                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 151                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 152                 },
 153 #endif
 154 #if SECOND_CPU
 155                 {
 156                         .node_id = 1,
 157                         .f0 = PCI_DEV(0, 0x19, 0),
 158                         .f1 = PCI_DEV(0, 0x19, 1),
 159                         .f2 = PCI_DEV(0, 0x19, 2),
 160                         .f3 = PCI_DEV(0, 0x19, 3),
 161                         .channel0 = { (0xa<<3)|4, 0, 0, 0 },
 162                         .channel1 = { (0xa<<3)|5, 0, 0, 0 },
 163                 },
 164 #endif
 165         };
 166         if (cpu_init_detected()) {
 167                 asm("jmp __cpu_reset");
 168         }
 169         enable_lapic();
 170         init_timer();
 171         if (!boot_cpu() ) {
 172 //              notify_bsp_ap_is_stopped();
 173                 stop_this_cpu();
 174         }
 175         uart_init();
 176         console_init();
 177         setup_default_resource_map();
 178         setup_coherent_ht_domain();
 179         enumerate_ht_chain(0);
 180         distinguish_cpu_resets(0);
 181
 182 #if 0
 183         print_pci_devices();
 184 #endif
 185         enable_smbus();
 186 #if 0
 187         dump_spd_registers(&cpu[0]);
 188 #endif
 189         memreset_setup();
 190         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 191
 192 #if 0
 193         dump_pci_devices();
 194 #endif
 195 #if 0
 196         dump_pci_device(PCI_DEV(0, 0x18, 1));
 197 #endif
 198
 199         /* Check all of memory */
 200 #if 0
 201         msr_t msr;
 202         msr = rdmsr(TOP_MEM2);
 203         print_debug("TOP_MEM2: ");
 204         print_debug_hex32(msr.hi);
 205         print_debug_hex32(msr.lo);
 206         print_debug("\r\n");
 207 #endif
 208 /*
 209 #if  0
 210         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 211 #else
 212 #if TOTAL_CPUS < 2
 213         // Check 16MB of memory @ 0
 214         ram_check(0x00000000, 0x01000000);
 215 #else
 216         // Check 16MB of memory @ 2GB
 217         ram_check(0x80000000, 0x81000000);
 218 #endif
 219 #endif
 220 */
 221 }