4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
15 #include "northbridge/amd/amdk8/incoherent_ht.c"
16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
17 #include "northbridge/amd/amdk8/raminit.h"
18 #include "cpu/amd/model_fxx/apic_timer.c"
19 #include "lib/delay.c"
20 #include "cpu/x86/lapic/boot_cpu.c"
21 #include "northbridge/amd/amdk8/reset_test.c"
22 #include "northbridge/amd/amdk8/debug.c"
23 #include "northbridge/amd/amdk8/cpu_rev.c"
24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
26 #include "cpu/x86/bist.h"
28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
30 static void hard_reset(void)
35 pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
40 static void soft_reset(void)
43 pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
45 static void soft2_reset(void)
48 pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
51 static void memreset_setup(void)
53 if (is_cpu_pre_c0()) {
54 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
57 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
59 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
62 static void memreset(int controllers, const struct mem_controller *ctrl)
64 if (is_cpu_pre_c0()) {
66 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
71 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
73 /* Routing Table Node i
75 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
76 * i: 0, 1, 2, 3, 4, 5, 6, 7
78 * [ 0: 3] Request Route
79 * [0] Route to this node
83 * [11: 8] Response Route
84 * [0] Route to this node
88 * [19:16] Broadcast route
89 * [0] Route to this node
95 uint32_t ret=0x00010101; /* default row entry */
96 /* Link1 of CPU0 to Link1 of CPU1 */
97 static const unsigned int rows_2p[2][2] = {
98 { 0x00050101, 0x00010404 },
99 { 0x00010404, 0x00050101 }
103 print_debug("this mainboard is only designed for 2 cpus\r\n");
108 if (!(node>=maxnodes || row>=maxnodes)) {
109 ret=rows_2p[node][row];
115 static inline void activate_spd_rom(const struct mem_controller *ctrl)
120 static inline int spd_read_byte(unsigned device, unsigned address)
122 return smbus_read_byte(device, address);
126 //#include "northbridge/amd/amdk8/setup_resource_map.c"
127 #include "northbridge/amd/amdk8/raminit.c"
128 #include "northbridge/amd/amdk8/coherent_ht.c"
129 #include "sdram/generic_sdram.c"
131 #include "northbridge/amd/amdk8/resourcemap.c"
135 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
136 static void main(unsigned long bist)
138 static const struct mem_controller cpu[] = {
142 .f0 = PCI_DEV(0, 0x18, 0),
143 .f1 = PCI_DEV(0, 0x18, 1),
144 .f2 = PCI_DEV(0, 0x18, 2),
145 .f3 = PCI_DEV(0, 0x18, 3),
146 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
147 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
153 .f0 = PCI_DEV(0, 0x19, 0),
154 .f1 = PCI_DEV(0, 0x19, 1),
155 .f2 = PCI_DEV(0, 0x19, 2),
156 .f3 = PCI_DEV(0, 0x19, 3),
157 .channel0 = { (0xa<<3)|4, 0, 0, 0 },
158 .channel1 = { (0xa<<3)|5, 0, 0, 0 },
166 /* Skip this if there was a built in self test failure */
167 amd_early_mtrr_init();
171 nodeid = lapicid() & 0xf;
173 if (cpu_init_detected(nodeid)) {
174 asm volatile ("jmp __cpu_reset");
176 distinguish_cpu_resets(nodeid);
182 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
186 /* Halt if there was a built in self test failure */
187 // report_bist_failure(bist);
189 setup_default_resource_map();
190 needs_reset = setup_coherent_ht_domain();
191 needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
193 print_info("ht reset -\r\n");
202 dump_spd_registers(&cpu[0]);
205 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
211 dump_pci_device(PCI_DEV(0, 0x18, 1));
214 /* Check all of memory */
217 msr = rdmsr(TOP_MEM2);
218 print_debug("TOP_MEM2: ");
219 print_debug_hex32(msr.hi);
220 print_debug_hex32(msr.lo);
225 ram_check(0x00000000, msr.lo+(msr.hi<<32));
228 // Check 16MB of memory @ 0
229 ram_check(0x00000000, 0x01000000);
231 // Check 16MB of memory @ 2GB
232 ram_check(0x80000000, 0x81000000);